Semiconductor memory array

Details Semiconductor memory array Semiconductor memory array

1999-12-01

2001-12-11

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

C257S206000, C257S208000, C257S390000, C257S909000, C257S910000

Reexamination Certificate

active

06329678

ABSTRACT:

This application claims the benefit of Korean Application No. 98-53130 filed Dec. 4, 1998, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory array. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for improving a packaging reliability, respective AC parameters, and device speed.
2. Description of the Related Art
FIG. 1
is a block diagram illustrating a related background art semiconductor memory array. As shown therein, a first Y decoder
12
-
1
and a first X decoder
11
-
1
are disposed at the lower end and the right side of a first memory mat MAT
1
, respectively. A second Y decoder
12
-
2
and the second X decoder
11
-
2
are disposed at the upper end and the right side of a second memory mat MAT
2
, respectively.
An array control region
13
is located between the first Y decoder
12
-
1
and the first X decoder
11
-
1
, and the second Y decoder
12
-
2
and the second X decoder
11
-
2
. A main amplifier region
20
is positioned at the right side of a memory mat region
10
including
6
he first and second memory mats MAT
1
, MAT
2
, the array control region
13
, the first and second X decoders
11
-
1
,
11
-
2
and the first and second Y decoders
12
-
1
,
12
-
2
.
A peripheral device region
30
is disposed to surround a region where the memory mat region
10
and the main amplifier region
20
are located. First and second pad regions
41
,
42
are respectively disposed at the left and right sides of the peripheral device region
30
to access the first and second memory mats MAT
1
, MAT
2
. Here, power pins are excluded from the first and second pad regions
41
,
42
.
The above described background art semiconductor memory array has the pad regions
41
,
42
disposed at both sides of the first and second memory mats MAT
1
, MAT
2
to access the first and second memory mats MAT
1
, MAT
2
. Thus, a device speed is decreased due to large chip size resulting from a higher integration.
FIG. 2
is a block diagram illustrating a background art LOC (lead-on-chip) type semiconductor memory array. As shown therein, first and second main amplifier regions
21
,
22
are disposed at the upper end and the lower end of first and second memory mat regions MAT
1
′, MAT
2
′, respectively. First and second peripheral device regions
31
,
32
are disposed adjacent to the first and second main amplifier regions
21
,
22
. A pad region
40
is located between the first and second peripheral. device regions
31
,
32
so as to access the first and second memory mat regions MAT
1
′, MAT
2
′. Here, power pins are excluded from the pad region
40
.
FIG. 3
is a block diagram illustrating a conventional 64M SDRAM array. As shown therein,
16
M bits of first to fourth mats MAT
1
, MAT
2
, MAT
3
, and MAT
4
are arrayed in a checkerboard pattern. First to fourth X decoders
11
-
1
,
11
-
2
,
11
-
3
, and
11
-
4
are disposed at the left or right side of the first to fourth memory mats MAT
1
, MAT
2
, MAT
3
, and MAT
4
. First to fourth Y decoders
121
,
12
-
2
,
12
-
3
, and
12
-
4
are disposed at the lower end or upper end of the first to fourth memory mats MAT
1
, MAT
2
, MAT
3
, and MAT
4
. First and second array control regions
13
-
1
,
13
-
2
are disposed between the first and second X decoders
11
-
1
,
11
-
2
and between the third and fourth X decoders
11
-
3
,
11
-
4
.
First and second main amplifier regions
21
,
22
are disposed at the lower end and the upper end of a first memory mat region
11
including the first and second memory mats MAT
1
, MAT
2
, the first and second X decoders
11
-
1
,
11
-
2
, the first and second Y decoders
12
-
1
,
12
-
2
and the first array control region
13
-
1
, and a second memory mat region
12
including the third and fourth memory mats MAT
3
, MAT
4
, the third and fourth X decoders
11
-
3
,
11
-
4
, the third and fourth Y decoders.
12
-
3
,
12
-
4
and the second array control region
13
-
2
.
First and second peripheral device regions
31
,
32
are disposed adjacent to the first and second main amplifier regions
21
,
22
, respectively. A pad region
40
is disposed between the first and second peripheral device regions
31
,
32
so as to access the first to fourth memory mats MAT
1
, MAT
2
, MAT
3
, and MAT
4
. Here, power pins are excluded from the pad region
40
.
FIG. 4
is a block diagram illustrating a conventional 128M SDRAM array. As shown therein,
16
M bits of first to eighth mats MAT
1
to MAT
8
are arrayed in a checkerboard pattern. First to eighth X decoders
11
-
1
to
11
-
8
are disposed at the left or right side of the first to eighth memory mats MAT
1
to MAT
8
. First to eighth Y decoders
12
-
1
to
12
-
8
are disposed at the lower end or upper end of the first to eighth memory mats MAT
1
to MAT
8
. First to fourth array control regions
13
-
1
to
13
-
4
are disposed between the first and second X decoders
11
-
1
,
11
-
2
, between the third and fourth X decoders
11
-
3
,
11
-
4
, between the fifth and sixth X decoders
11
-
5
,
11
-
6
, and between the seventh and eighth X decoders
11
-
7
,
11
-
8
.
Here, a first memory mat region
11
includes the first and second memory mats MAT
1
, MAT
2
, the first and second X decoders
11
-
1
,
11
-
2
, the first and second Y decoders
12
-
1
,
12
-
2
, and the first array control region
13
-
1
. Likewise, second to fourth memory mat regions
12
to
14
include memory mats, X decoders, Y decoders, and array control regions. First and second main amplifier regions
21
,
22
are disposed at the upper end and the lower end of the second memory mat region
12
and the third memory mat region
13
, respectively. First and second peripheral device regions
31
,
32
are disposed at the upper end and the lower end of the first and second main amplifier regions
21
,
22
. A pad region
40
is disposed between the first and second peripheral device regions
31
,
32
so as to access the first to eight memory mats MAT
1
to MAT
8
. Here, power pins are excluded from the pad region
40
.
FIG. 5
is a block diagram illustrating another conventional 128M SDRAM array. As shown therein, 16M bits of first to eighth mats MAT
1
to MAT
8
are arrayed in a checkerboard pattern. First to eighth X decoders
11
-
1
to
11
-
8
are disposed at the left or right side of the first to eighth memory mats MAT
1
to MAT
8
. First to eighth Y decoders
12
-
1
to
12
-
8
are disposed at the upper end or lower end of the first to eighth memory mats MAT
1
to MAT
8
. First and fourth array control regions
13
-
1
to
13
-
4
are disposed between the first and second X decoders
11
-
1
,
11
-
2
, between the third and fourth X decoders
11
-
3
,
11
-
4
, between the fifth and sixth X decoders
11
-
5
,
11
-
6
, and between the seventh and eighth X decoders
11
-
7
,
11
-
8
, respectively.
Here, a first memory mat region
11
includes the first and second memory mats MAT
1
, MAT
2
, the first and second X decoders
11
-
1
,
11
-
2
, the first and second Y decoders
12
-
1
,
12
-
2
, and the first array control region
13
-
1
. Likewise, second to fourth memory mat regions
12
to
14
include memory mats, X decoders, Y decoders, and array control regions.
First to fourth main amplifier regions
21
to
24
are disposed at the upper end and the lower end of the first to fourth memory mat regions
11
to
14
. A peripheral device region
30
is disposed between the third and fourth memory mat regions
11
,
12
and the third and fourth memory mat regions
13
,
14
. A pad region
40
is disposed within the peripheral device regions between the first and second peripheral device regions
31
,
32
so as to access the first to eight memory mats MAT
1
to MAT
8
. Here, power pins are excluded from the pad region
40
.
When fabricating a 128M DRAM in accordance with the present design rule (i.e., 0.023 &mgr;m of line w

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