Semiconductor memory arrangement

Details Semiconductor memory arrangement Semiconductor memory arrangement

2007-05-31

2011-10-18

Phung, Anh (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C710S305000

Reexamination Certificate

active

08040710

ABSTRACT:
A semiconductor memory arrangement includes a circuit board having at least a first layer and a second layer, a plurality of memory units, and a first control device and a second control device adapted to receive command and address signals. A first bus system is disposed in the first layer of the circuit board and coupled to the first control device and to a first group of memory units of the plurality of memory units to transmit the command and address signals to the first group of memory units. A second bus system is disposed in the second layer of the circuit board and coupled to the second control device and to a second group of memory units of the plurality of memory units to transmit the command and address signals to the second group of memory units.

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