Semiconductor memory apparatus with reduced line widths

Details Semiconductor memory apparatus with reduced line widths Semiconductor memory apparatus with reduced line widths

1991-06-12

1994-12-20

Callahan, Timothy P.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 365226, 36518909, 365196, 327 51, G11C 800, G11C 700

Patent

active

053750950

ABSTRACT:
A dynamic random access memory is formed with two power supply meshes extending throughout a memory array region in which are formed memory cells and sense amplifier circuits, thereby enabling sense amplifier drive circuits to be distributed throughout that memory array region, with each sense amplifier drive circuit being connected to the nearest points on the two supply meshes. A substantially improved value of read access time, or increased total memory capacity, can thereby be achieved by comparison with a DRAM in which the sense amplifier drive circuits are provided only at the periphery of a memory array region.

REFERENCES:
patent: 4761571 (1988-08-01), Golke et al.
patent: 4980799 (1990-12-01), Tobita
patent: 5040144 (1991-08-01), Pelley et al.
patent: 5072425 (1991-12-01), Kohno et al.
patent: 5231607 (1993-07-01), Yoshida et al.

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