Semiconductor memory apparatus with a delay locked loop circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Details

C327S161000

Reexamination Certificate

active

07605623

ABSTRACT:
A semiconductor memory apparatus includes a delay line configured to delay a reference clock, a first delay block configured to delay a feedback clock, a first phase comparator configured to compare the reference clock with an output of the first delay block, a second delay block configured to delay the reference clock, a second phase comparator configured to compare the feedback clock with an output of the second delay block, a delay controller configured to control a delay amount of the delay line based on comparison results from the first and second phase comparators, a delay model configured to delay an output of the delay line by a modeled delay time to generate the feedback clock, and a locking detector configured to control the delay controller based on comparison results from the first and second phase comparators.

REFERENCES:
patent: 6813197 (2004-11-01), Park
patent: 6956418 (2005-10-01), Kwak et al.
patent: 6989700 (2006-01-01), Kim
patent: 7103133 (2006-09-01), Jung
patent: 7154311 (2006-12-01), Lim
patent: 7170313 (2007-01-01), Shin
patent: 2004/0085107 (2004-05-01), Kwak et al.
patent: 2005/0110540 (2005-05-01), Kwak
patent: 2005/0195663 (2005-09-01), Kwak
patent: 2006/0267649 (2006-11-01), Park et al.
patent: 2005-251370 (2005-09-01), None
patent: 2001-0044876 (2001-06-01), None
patent: 10-2004-0046328 (2004-06-01), None
patent: 10-2004-0095981 (2004-11-01), None
patent: 10-2006-0095260 (2006-08-01), None

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