Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-03-27
2002-07-23
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180
Reexamination Certificate
active
06424572
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory apparatus. More particularly, the present invention relates to a non-volatile memory.
2. Description of the Related Art
In recent years, a non-volatile memory constituted by non-volatile memory cells having floating gates has been vigorously developed. As shown in
FIG. 1
, a conventional non-volatile memory is provided with a word line W
1
, a word line W
2
, an X-decoder
41
, a bit line B
1
, a bit line B
2
, output signals Y
1
, Y
2
, a sense amplifier
43
, an N-channel transistor N
1
, an N-channel transistor N
2
, an N-channel transistor N
3
, an N-channel transistor N
4
, a P-channel transistor P
1
and a P-channel transistor P
2
.
The word line W
1
is connected to the control gates of memory cells MC
1
, MC
2
. The word line W
2
is connected to the control gates of memory cells MC
3
, MC
4
. The X-decoder
41
is connected to the word lines W
1
, W
2
. The bit line B
1
is connected to drains of the memory cells MC
1
, MC
3
. The bit line B
2
is connected to drains of the memory cells MC
2
, MC
4
. The output signals Y
1
, Y
2
are connected to a Y-decoder
42
. The sense amplifier
43
receives a pre-charge signal PRECH. The N-channel transistor N
1
is connected to the bit line B
1
and the sense amplifier
43
, and receives from a gate thereof the output signal Y
1
. The N-channel transistor N
2
is connected to the bit line B
2
and the sense amplifier
43
, and receives from a gate thereof the output signal Y
2
. The N-channel transistor N
3
is connected to the bit line B
1
and a GND power supply, and receives from a gate thereof a discharge signal DIS. The N-channel transistor N
4
is connected to the bit line B
2
and the GND power supply, and receives from a gate thereof the discharge signal DIS. The P-channel transistor P
1
is connected to the bit line B
1
and a VDD power supply, and receives from a gate thereof an input signal DW
1
. And, the P-channel transistor P
2
is connected to the bit line B
2
and the VDD power supply, and receives from a gate thereof an input signal DW
2
.
Each of the memory cells MC
1
to MC
4
is a non-volatile memory cell having the control gate and the floating gate. A threshold of the memory cell is controlled on the basis of an amount of electrons sent to the floating gate.
For example, when the electrons are implanted into the floating gate, its threshold VTM becomes high. For example, it is set to 6 V. Also, if the electrons are drawn out from the floating gate, its threshold VTM becomes low. For example, it is set to 2 V.
Here, if the threshold VTM of the memory cell is high (for example, VTM=6 V) so that the memory cell is sufficiently turned off even when a voltage to read a data stored in the memory cell, for example, 4 V is applied to the word line, it is assumed that a data “0” is stored in its memory cell. If the VTM is low (for example, VTM=2 V) so that the memory cell is sufficiently turned on, it is assumed that a data “1” is stored in the memory cell.
A write circuit
44
has the P-channel transistors P
1
, P
2
. It sets the input signal DW
1
or DW
2
at a low level at a time of a writing operation, and supplies the VDD power supply through the transistor P
1
or P
2
to the bit line B
1
or B
2
.
The sense amplifier
43
receives the pre-charge signal PRECH. When its signal becomes at a high level, it supplies 1 V as a pre-charge level to the N-channel transistors N
1
, N
2
.
The operation for reading the data stored in the memory cell in this conventional example will be described below with reference to timing charts of
FIGS. 2A
to
2
I.
By the way, let us suppose that the data “0” is stored in the memory cells MC
1
, MC
2
, and the data “1” is stored in the memory cells MC
3
, MC
4
. It is assumed to read the data in the memory cell MC
1
.
At first, the bit lines B
1
, B
2
are discharged (a period ti). So, the output signals Y
1
, Y
2
of the Y-decoder
42
are set to the low level, and the discharge signal DIS is set to the high level. The input signals DW
1
, DW
2
are set to the high level. Thus, the N-channel transistors N
1
, N
2
are turned off. The N-channel transistors N
3
, N
4
are turned on. The P-channel transistors P
1
, P
2
are turned off. And, the bit lines B
1
, B
2
are set to the GND level.
Next, a selected bit line (here, the bit line B
1
) is pre-charged (a period t
2
). So, the output signal Y
1
is set to the high level, and the output signal Y
2
is set to the low level. The pre-charge signal PRECH is set to the high level, and the discharge signal DIS is set to the low level. Thus, the N-channel transistors N
2
to N
4
are turned off, and the N-channel transistor N
1
is turned on. Hence, 1 V implying the pre-charge level is supplied to the bit line B
1
through the transistor N
1
from the sense amplifier.
Next, a voltage to carry out the reading operation is supplied to a word line (here, the word line W
1
) of the memory cell to be selected, and a sampling is carried out (a period t
3
). To do so, the pre-charge signal PRECH is set to the low level. The word lines W
1
, W
2
are switched to the high level (for example, 4 V), and the low level (for example, 0 V), respectively. Thus, 1 V is supplied to the drain of the memory cell MC
1
, and 4 V is supplied to the control gate. Then, the stored data is sampled. Since the data “0” is stored in the memory cell MC
1
, a current does not flow through the memory cell MC
1
. Hence, a potential of the bit line is not changed, and it is kept at 1 V. Its level as the data “0” is detected by the sense amplifier
43
. By the way, if the data “1” is stored in the memory cell, the current flows through the memory cell. Hence, the potential of the bit line is changed from 1 V to 0.9 V. Its changed level as the data “1” is detected by the sense amplifier
43
. The operation for reading the memory cell MC
1
is ended after the above-mentioned operations.
In the reading operation, the potential of the bit line is once set to the GND level by the discharge operation. After that, it is pre-charged to 1 V. Thus, when the data “1” is sampled, the time required to change the potential of the bit line from 1 V to 0.9 V is reduced to thereby enable the reading operation to be made faster.
However, even in the discharge operation, as the potential of the bit line is higher, it is necessary to make the discharge period longer. Although 4 V is applied to the word line W
1
at the time of the sampling of the memory cell MC
1
, the data “0” is stored in the memory cell MC
2
. So, the memory cell MC
2
is at the off-state. For this reason, if a leakage current exists in the P-channel transistor P
2
in the write circuit
44
, the bit line B
2
is charged by the leakage current during the sampling of the memory cell MC
1
. Thus, there may be a possibility that the potential of the bit line B
2
is raised up to a maximum VDD level. Also, since the data stored in the memory cell MC
1
is at “0”, the memory cell MC
1
is at the off-state. Hence, even the bit line B
1
is similarly charged by the leakage current, and there may be a possibility that it is raised up to the maximum VDD level.
In order to read the memory cell MC
2
after reading the memory cell MC
1
, the bit line is discharged (a period t
4
). However, there may be a possibility that the potential of the bit line B
2
is equal to or greater than 1 V implying an expectation value (an over-discharge state). Thus, in order to surely discharge the bit line, it is necessary to make the discharge period longer. Hence, the conventional non-volatile memory has the problem of the impediment against the higher speed of the reading operation.
Japanese Laid Open Patent Application (JP-A-Heisei, 10-64289) discloses the following non-volatile memory. In the non-volatile memory containing: a memory cell array in which memory cells arrayed in a form of rows and columns are mounted; and a row decoder having voltage supply transistor circuits for supplying voltages to the control gates of
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