Static information storage and retrieval – Powering
Reexamination Certificate
2000-08-04
2003-01-07
Zarabian, Amir (Department: 2824)
Static information storage and retrieval
Powering
C365S227000
Reexamination Certificate
active
06504782
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory apparatus. More particularly, the present invention relates to a semiconductor memory apparatus that can prevent a write level of data to a memory cell from dropping and improve a sense speed at a next cycle.
2. Description of the Related Art
A memory capacity or storage capacity of DRAM has increased year by year, which has promoted a hyperfine structure of MOSFET. So, in order to insure the reliability of a transistor and reduce the consumptive electric power, a solution is employed for generating a step-down power supply of a certain level from an external power supply to use as a power supply in an inner circuit.
In this case, a power supply having the same level is used in a memory cell array section and a write amplifier for sending a write data inputted from an external portion to the memory cell array section.
Here, if a plurality of banks exist in the memory cell array section, and at the same time, one bank is at a low active state and in another bank a write operation can be carried out, and a part of or all of the plurality of banks are memories using the same power supply, a sense noise and a noise when the write amplifier is actuated have influence on the inner step-down power supply. Thus, it is difficult to maintain the step-down power supply level.
If the power supply level is dropped or reduced, a re-write level of a data, which is read out from a cell at the time of the actuation of the sense amplifier, to the cell is dropped that causes the deterioration of a speed when the cell data is read out.
Japanese Laid Open Patent Application (JP-A-Heisei, 10-55667) discloses the following semiconductor memory apparatus. This is provided with: a first inner voltage generator for supplying a voltage to a condenser of a memory cell; an inner voltage step-down circuit for supplying an operational power supply voltage to respective circuit sections except the memory section; and a second inner voltage generator for generating a voltage to amplify a signal read out on a bit line. Apart from a drive voltage of each circuit, it is possible to make a voltage of a signal that is re-written by a self-refresh higher to make a charge retaining performance higher and thereby enlarge an inner operation period of the self-refresh. The separation between a voltage to amplify a signal with regard to a memory information and a voltage to drive a transistor in the circuit enables the enlargement of the self-refresh period and the reduction of a consumptive current in one self-refresh operation. Hence, it is possible to reduce the consumptive electric power at a time of the operation in the self-refresh.
WO 97/24729 discloses the following dynamic type RAM. This generates a first inner voltage so as to provide a difference substantially equal to a threshold voltage of an address selection MOSFET of a dynamic type memory cell with respect to a power supply voltage, and sends as an operation voltage on a high level side to a sense amplifier. Also, this generates a second inner voltage so as to provide a predetermined difference from a ground potential of a circuit, and sends as an operation voltage on a low level side to the sense amplifier. Then, a write signal having a high level corresponding to the first inner voltage and a low level corresponding to the second inner voltage is generated by a write amplifier, and transmitted to a complementary data line to which the dynamic type memory cell is connected. So, the high level such as the power supply voltage as a selection level and the low level such as the ground potential of the circuit as a non-selection level are sent to a word line to which the dynamic type memory cell is connected.
Also, the WO 97/24729 discloses the following items. A sense amplifier and a write buffer circuit are driven by receiving an inner voltage VSG and an inner voltage VDL generated by a voltage generator composed of a VSG voltage generator and a VDL voltage generator. The write buffer circuit is a circuit for writing the information of the high level or the low level to the respective memory cells in a memory mat.
The sense amplifier has a pair of input and output nodes connected to the complement bit lines, and amplifies a read out signal of a micro signal level, which is read out to a corresponding bit line from the memory cell selected by the word line selection, to a high level or a low level. The sense amplifier also amplifies a signal applied to the bit line from the write circuit when a data is written so that the signal becomes at predetermined high and low levels at an early time. Thus, the data read out from the selected memory cell is again written through the bit line to the memory cell after a level of the data is recovered by the amplification operation of the sense amplifier. Also, the write data is amplified by the sense amplifier to be written to the memory cell after its level is changed into a high level and a low level of a predetermined level.
Japanese Laid Open Patent Application (JP-A-Heisei, 10-302492) discloses the following semiconductor integrated circuit apparatus. This is provided with: a booster
1
for boosting an external power supply voltage Vccext; a level detector for detecting a voltage variation of a boosting voltage Vccint; an inner voltage generator for generating an inner voltage Vccint based on the boosting voltage Vccint; an address buffer; an address decoder; and a memory cell array having an EEPROM configuration. The level detector has a first level detector for detecting a level at a time of a memory access and a second level detector for detecting a level at a time of standby. At the standby, the inner voltage generator short-circuits the boosting voltage Vccint and the inner voltage Vccint. The second level detector is smaller in consumptive electric power than the first level detector. Thus, the consumptive electric power at the standby can be reduced without the drop of a drive voltage.
Japanese Laid Open Patent Application (JP-A-Heisei, 5-334879) discloses the following semiconductor memory apparatus This is provided with a step-down circuit for generating an inner power supply voltage Vint and a standby mode judging circuit for monitoring the inner power supply voltage Vint. The step-down circuit has a compensation driver circuit in addition to an active driver circuit and a standby driver circuit. The compensation driver circuit compensates a component corresponding to a current increase in an inner circuit at the standby mode. Thus, this does not require a power cut function required in the conventional technique in order to protect the increase of the current in the inner circuit. Moreover, this avoids a drop of the inner power supply voltage Vint that is liable to occur at this time. Hence, the semiconductor memory apparatus of the present invention is operated stably at a high speed.
Japanese Laid Open Patent Application (JP-A-Heisei, 7-57472) discloses the following semiconductor integrated circuit apparatus. This is provided with: a receiver circuit for making a level of a first output signal have a two-value state based on a level of a write enable signal of SRAM; a switching circuit for switching a level of a second output signal to any one of an external power supply voltage and a value equal to a predetermined inner power supply voltage based on the level of the first output signal; and a step-down circuit for generating a voltage having a value equal to the level of the second output signal of the switching circuit from an external power supply voltage, and sending to an inner signal processor. Then, a reference voltage having a level lower than an “L” level of the write enable signal when the SRAM is usually operated is applied to another input end of the receiver circuit.
SUMMARY OF THE INVENTION
The present invention is accomplished in view of the above mentioned problems. Therefore, an object of the present invention is to provide a semiconductor memory apparatus that can prevent
Nguyen Van-Thu
Zarabian Amir
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