Semiconductor memory apparatus and method for outputting data

Details Semiconductor memory apparatus and method for outputting data Semiconductor memory apparatus and method for outputting data

2001-04-10

2002-12-17

Nelms, David (Department: 2818)

Static information storage and retrieval

Read only systems

Semiconductive

C365S063000, C365S230030

Reexamination Certificate

active

06496405

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to a semiconductor memory device and more particularly to a semiconductor memory device and a method of detecting cell current for outputting data during a read operation.
BACKGROUND OF THE INVENTION
In order to reduce the chip size of a read only memory (ROM), memory array architecture can be based on a flat cell. A flat cell may not have element isolation regions in the cell array. Thus, memory cells along a row can be connected in series.
Referring now to
FIG. 7
, a conventional ROM having a cell array using a flat cell is set forth in a block schematic diagram and designated by the general reference character
700
. Conventional ROM
700
includes a memory array
701
, a sense amplifier
702
, a y-selector
703
, precharge circuits
704
, a virtual ground (VG) selector
705
, and a x-decoder
706
.
The example illustrated in
FIG. 7
is a read operation of a memory cell connected to digit line D
2
and located between digit lines D
2
and D
1
. In the read operation, based on an applied y-address, Y-selector
703
selectively connects a main digit line (in this example D
2
) to a sense amplifier
702
and selectively connects an adjacent main digit line (in this example D
3
) to precharge circuit
704
. At this same time VG selector
705
connects virtual ground line VG
1
to ground and virtual ground line VG
2
to precharge circuit
704
.
Referring now to
FIG. 8
, a circuit schematic wiring diagram of the y-selector
703
of
FIG. 7
is set forth. Y-selector includes a data selection section
802
and a precharge section
804
.
Data selection section
802
includes data selection circuits (
806
and
806
′). It is understood that there are many data selection circuits but only data selection circuits (
806
and
806
′) are illustrated to avoid unduly cluttering the figure. Each data selection circuit operates in the same manner, thus only data selection circuit
806
will be discussed. Data selection circuit
806
receives y-selection signals (Y
0
to Y
7
). Data selection circuit
806
includes data selection transistors (TD
0
to TD
7
) connected between digit lines (D
0
to D
7
) respectively and sense amplifer
702
. Each data selection transistor (TD
0
to TD
7
) receives a respective y-selection signal (Y
0
to Y
7
) and selectively connects a digit line to a respective sense amplifier
702
. In this case, y-selection signal Y
2
, is active (high), thus data selection transistor TD
2
is conductive and electrically connects digit line D
2
to sense amplifier
702
. Thus, a data bit from a cell (not shown in
FIG. 8
) connected to digit line D
2
is accessed. In this case, all other digit lines in the digit line group (D
0
, D
1
, and D
3
to D
7
) are not connected to sense amplifier
702
because their corresponding data selection transistor (TD
0
, TD
1
, and TD
3
to TD
7
) are turned off.
Precharge section
804
includes precharge selection circuits (
808
and
808
′). It is understood that there are many precharge selection circuits but only precharge selection circuits (
808
and
808
′) are illustrated to avoid unduly cluttering the figure. Each precharge selection circuit operates in the same manner, thus only data selection circuit
808
will be discussed. Precharge selection circuit
808
receives precharge selection signals (P
0
to P
7
). Precharge selection circuit
808
includes precharge selection transistors (TP
0
to TP
7
) connected between digit lines (D
0
to D
7
) respectively and precharge circuit
704
. Each precharge selection transistor (TP
0
to TP
7
) receives a respective precharge selection signal (P
0
to P
7
) and selectively connects a digit line to precharge circuit
704
. In this case, precharge selection signal P
3
, is active (high), thus precharge selection transistor TP
3
is conductive and electrically connects digit line D
3
to precharge circuit
704
. Thus, digit line D
3
is precharged when a data bit from a cell (not shown in
FIG. 8
) connected to adjacent digit line D
2
is accessed. In this case, all other digit lines in the digit line group (D
0
, D
1
, D
2
and D
4
to D
7
) are not connected to precharge circuit
704
because their corresponding precharge selection transistor (TD
0
, TD
1
, TD
2
, and TD
4
to TD
7
) are turned off.
Referring now to
FIG. 9
, a circuit diagram showing an operating state of conventional semiconductor memory device
700
is set forth. For simplicity, the circuit diagram of
FIG. 9
, illustrates only a portion of the memory cell array
702
corresponding to digit lines (D
2
to D
5
)
The conventional semiconductor memory
700
of
FIG. 9
, illustrates a read from memory cell
910
. Memory cell
910
has been programmed with a low threshold voltage, such that when word line W
01
is high, memory cell
910
is conductive or is an on-bit cell. Memory cells that are not conductive (off-bit cell) when their respective word line is high are denoted with an “X”. It can be seen that the memory cell adjacent to memory cell
910
and commonly connected to sub-digit line D
22
is an off-bit cell.
FIG. 10
sets forth a truth table illustrating logic levels of y-selection signals (Y
0
to Y
7
), precharge selection signals (P
0
to P
7
), bank selection signals (BS
0
and BS
1
) and ground selection lines (GS
0
to GS
3
) when a predetermined memory cell column is selected. In the example illustrated in
FIG. 9
, memory cell
910
is selected. Memory cell
910
is in a memory cell column that corresponds with digit line D
2
and BANK
2
. Thus, y-selection signal Y
2
, precharge signal P
3
, bank selection signal BS
1
, and ground selection line GS
1
are all enabled (high).
When memory cell
910
is selected, word line W
01
goes high and y-selection signal Y
2
, precharge signal P
3
, bank selection signal BS
1
, and ground selection line GS
1
are all high. Also, main virtual ground line VG
1
is connected to ground and main virtual ground line VG
2
is connected to a precharge potential through precharge circuit
704
. In this manner, selected memory cell
910
has a source electrically connected to ground through a VG selection transistor
902
and a drain electrically connected to sense amplifier
702
through bank selection transistor
906
and data selection transistor TD
2
.
In the case illustrated in
FIG. 9
, the cell adjacent to memory cell
910
is an off-cell, thus current flowing from precharge circuit
704
through the row of memory cells connected to word line W
01
is blocked from sub-digit line D
22
and memory cell
910
. Therefore, in this case, a steady-state current ISA flowing through selected cell
910
is the same as the current flowing through digit line D
2
and sensed by sense amplifier
702
.
Referring now to
FIG. 11
, a circuit diagram showing an operating state of conventional semiconductor memory device
700
is set forth. The circuit diagram of
FIG. 11
, illustrates a case where the memory cell adjacent to selected memory cell
910
is an on-bit cell. In this case, selected memory cell
910
provides a current path from ground to sense amplifier
702
, shown as ISA. However, selected memory cell
910
also provides current paths from ground to precharge circuit
704
. These undesirable current paths are illustrated by dashed lines, where IPC
0
is a current path to precharge circuit
704
through digit line D
3
and IPC
1
is a current path to precharge circuit
704
through VG selection transistor
904
. In this case, the current flowing through selected cell
910
is given by the sum of current ISA
0
flowing through selected digit line D
2
and the currents IPC
0
and IPC
1
flowing from precharge circuit
704
.
 
ISA=ISA
0
+
IPC
0
+
IPC
1
Referring now to
FIG. 12
, a graph is shown illustrating a simulation of currents in the memory cell configurations of
FIGS. 9 and 11
over a range of operating voltages.
Waveform
1202
illustrates the current ISA as shown in
FIG. 9
in which the cell adjacent to selected cell
910
is an off-bit cell. Waveform
1204
i

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