Semiconductor memory apparatus

Static information storage and retrieval – Addressing – Sync/clocking

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Details

36518905, 36523008, G11C 11413

Patent

active

052688739

ABSTRACT:
A ROM apparatus includes a control circuit for controlling an output buffer to be turned into a high impedance state or an off state for a predetermined time in response to a change of an address signal. For this control circuit, a supply of data read from a wrong address of a memory to an external circuit is prohibited for a duration of a false malfunction which is caused by a precharge of digit lines.

REFERENCES:
patent: 4537147 (1986-02-01), Aoyama et al.
patent: 4982366 (1991-01-01), Takemae

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