Semiconductor memory apparatus

Static information storage and retrieval – Floating gate – Particular biasing

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36518513, 3651852, 36518523, G11C16/06

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active

059056762

ABSTRACT:
It is an object of the present invention to provide a semiconductor memory apparatus that provides a large determination margin for reading operation. A semiconductor memory apparatus includes a memory cell array having a common source line disposed between first memory cells and second memory cells, a comparison cell pair (first and second comparison cells) and a read circuit. The comparison cells are formed by the same manufacturing process as that of the memory cells. The read circuit includes a comparison cell selection circuit for selecting one of the comparison cells. When a memory cell is read, the comparison cell selection circuit selects one of the comparison cells that corresponds to the memory cell. A plurality of comparison cell pairs may be provided and comparison cells thereof may be connected in parallel with one another. In this case, the size of each transistor of a current mirror circuit included in a sense amplifier is adjusted in accordance with the number of the comparison cell pairs. The semiconductor memory apparatus is applicable to memories whose source and drain regions are formed by diagonal ion implantation.

REFERENCES:
patent: 4636979 (1987-01-01), Donoghue
patent: 5386158 (1995-01-01), Wang
patent: 5386388 (1995-01-01), Atwood et al.
patent: 5621686 (1997-04-01), Alexis
patent: 5684739 (1997-11-01), Takeuchi

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