Semiconductor memory and test method incorporating selectable cl

Details Semiconductor memory and test method incorporating selectable cl Semiconductor memory and test method incorporating selectable cl

1996-01-11

1999-04-06

Nguyen, Hoa T.

Excavating

324 731, G11C 2900

Patent

active

058927760

ABSTRACT:
A semiconductor memory is provided with a select circuit and a control circuit. The select circuit selects either a master clock signal or a test clock signal supplied to a specific terminal, based upon a mode selection signal supplied to a specific terminal. The control operation writes, reads and erases data of the memory cells in response to the master clock signal or the test clock signal. A semiconductor memory test method includes a number of steps, including supplying a mode selection signal, which is higher than normally used voltage, to a specific terminal, and a test clock signal is supplied to another specific terminal; the master clock signal and the test clock signal are then switched in response to the mode selection signal; the data writes and erases relating to the cells of the memory are then tested based upon the test clock signal. In other semiconductor memory test method, two or more specific terminals are first selected, and are supplied with a mode selection signal which is higher than a normally used voltage; then, a master clock signal with a predetermined frequency is selected based upon the mode selection signal. The data writes and erases relating to the cells of the memory are tested based upon the master clock signal with the predetermined frequency.

REFERENCES:
patent: 4697140 (1987-09-01), Saito et al.
patent: 4747079 (1988-05-01), Yamaguchi
patent: 4866544 (1989-09-01), Hashimoto
patent: 4965799 (1990-10-01), Green et al.
patent: 5285409 (1994-02-01), Hwanngbo et al.
patent: 5453993 (1995-09-01), Kitaguchi et al.
Patent Abstracts Of Japan, Japanese Kokai Publication No. 61-258399 A, published Nov. 15, 1986, "Semiconductor Integrated Circuit Device", Yoshihiro et al.
Patent Abstracts of Japan, Japanese Kokai Publication No. 60-001700 A, published Jan. 7, 1985, "Pseudo Static Memory Circuit", Kazuo.

Affiliated with

Also associated with

Rating

Semiconductor memory and test method incorporating selectable cl does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory and test method incorporating selectable cl, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory and test method incorporating selectable cl will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1377862