Semiconductor memory and method of writing, reading, and sustain

Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Bipolar transistor

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Details

257201, 257105, 365180, H01L 29201, H01L 29737, G11C 1140

Patent

active

058641521

ABSTRACT:
A semiconductor memory has bit lines, word lines, ground lines, and memory cells. The bit lines intersect the word and ground lines, to form intersections where the memory cells are arranged, respectively. Each of the memory cells consists of a double-emitter transistor. This transistor has a collector, a first emitter, and a second emitter. Each base-emitter junction of the transistor has an N-shaped negative differential current-voltage characteristic that shows a relatively small gain up to a peak current and a relatively large gain after a valley current. The first emitter of each transistor is connected to a corresponding one of the ground lines. The second emitter is connected to a corresponding one of the word lines. The collector is connected to a corresponding one of the bit lines. Each of the memory cells has a small number of elements and requires only a small area.

REFERENCES:
patent: 5311465 (1994-05-01), Mori et al.
patent: 5438539 (1995-08-01), Mori
patent: 5561306 (1996-10-01), Imamura et al.
patent: 5574683 (1996-11-01), Mori

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