Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-06-09
2002-05-14
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185010, C257S315000
Reexamination Certificate
active
06388922
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory and a method of operating a semiconductor memory.
2. Description of the Prior Art
In recent years, a nonvolatile semiconductor memory such as an EPROM (erasable and programmable read only memory) or an EEPROM (electrically erasable and programmable read only memory) is watched with interest as a semiconductor memory capable of substituting for a hard disk or a floppy disk serving as a magnetic memory.
In a memory cell of an EPROM or an EEPROM, carriers are stored in a floating gate electrode for storing data by presence/absence of the carriers and reading data by detecting change of a threshold voltage following presence/absence of carriers. In particular, the EEPROM includes a flash EEPROM erasing data in a memory cell array as a whole or dividing the memory cell array into arbitrary blocks and erasing data in units of the respective blocks. The flash EEPROM, also referred to as a flash memory, capable of attaining a large capacity, low power consumption and a high-speed operation with excellent impact resistance is applied to various types of portable apparatuses. Further, the flash EEPROM having memory cells each formed by a single transistor can be readily integrated as compared with the EEPROM.
In general, a stacked gate memory cell and a split gate memory cell are proposed for forming the flash EEPROM.
In a write operation of storing electrons in a floating gate electrode of the stacked gate memory cell, electrons contained in a channel of a semiconductor substrate are converted to hot electrons and injected into the floating gate electrode. At this time, a voltage of ten-odd volts must be applied to a control gate electrode. In an erase operation of extracting electrons stored in the floating gate electrode of the stacked gate memory cell, a Fowler-Nordheim tunnel current (hereinafter referred to as an FN tunnel current) is fed from a drain region to the floating gate electrode. At this time, a voltage of ten-odd volts must be applied to the drain region.
In a write operation of storing electrons in a floating gate electrode of the split gate memory cell, electrons contained in a channel of a semiconductor substrate are converted to hot electrons and injected into the floating gate electrode. At this time, a voltage of ten-odd volts must be applied to a drain region. In an erase operation of extracting electrons stored in the floating gate electrode of the split gate memory cell, an FN tunnel current is fed from a control gate electrode to the floating gate electrode. At this time, a voltage of ten-odd volts must be applied to the control gate electrode.
Thus, in the conventional stacked gate or split gate memory cell, electrons are injected into the floating gate electrode as hot electrons in the write operation, and the electrons stored in the floating gate electrode are extracted through the FN tunnel current in the erase operation.
In order to hold carriers stored in the floating gate electrode over a long period of time, the thickness of an insulator film enclosing the floating gate electrode must be increased. However, the electrons are injected into or extracted from the floating gate electrode as hot electrons or through the FN tunnel current. Therefore, the voltage (hereinafter referred to as the operating voltage of the memory cell) applied to the control gate electrode or the drain region in the write or erase operation must be increased as the thickness of the insulator film enclosing the floating gate electrode is increased.
A step-up circuit generates the operating voltage of the memory cell. In this case, the step-up circuit can practically generate a voltage of up to ten-odd volts. When employing a silicon oxide film as the insulator film enclosing the floating gate electrode, the thickness of this silicon oxide film cannot exceed 8 to 10 nm assuming that the operating voltage of the memory cell is ten-odd volts. In general, therefore, the thickness of the silicon oxide film employed as the insulator film enclosing the floating gate electrode is set to 8 to 10 nm, in order to suppress the operating voltage of the memory cell to ten-odd volts. When the thickness of the silicon oxide film is about 8 to 10 nm, electrons stored in the floating gate electrode can be held for a period practically satisfactory to some extent.
Also when storing holes in the floating gate electrode, the thickness of the silicon oxide film forming the insulator film enclosing the floating gate electrode is set to 8 to 10 nm similarly to the aforementioned case of storing electrons, thereby suppressing the operating voltage of the memory cell to ten-odd volts and holding the holes stored in the floating gate electrode for a period practically satisfactory to some extent.
The feature of the flash memory resides in that cells sharing a word line are temporarily subjected to batch erasing and thereafter subjected to rewriting. In relation to the memory cell array, a structure operable with a small number of contacts is employed in order to improve the degree of integration.
Recently, the flash EEPROM is also required to attain a lower voltage, operations at a higher speed, lower power consumption and higher integration while attaining a longer life by increasing the period for holding carriers stored in the floating gate electrode.
When forming the insulator film enclosing the floating gate electrode by the silicon oxide film having the thickness generally set to 8 to 10 nm as described above, the thickness of the silicon oxide film must not be reduced below 8 nm, in order to attain a long life.
When reducing the operating voltage of the memory cell, the time (lead time) for stepping up the voltage is so reduced that the write and erase operations can be performed at a higher speed. Further, power consumption can also be reduced.
The circuit scale of the step-up circuit for generating the operating voltage of the memory cell is increased as the generated voltage is increased. The occupied area (transistor size) of a transistor forming a peripheral circuit, such as a decoder, a sense amplifier or a buffer, of the flash EEPROM is increased on the substrate as the voltage resistance thereof is increased. When reducing the operating voltage of the memory cell, therefore, the circuit scale of the step-up circuit as well as the size of the transistor forming the peripheral circuit are reduced, whereby higher integration can be attained.
Thus, operations at a higher speed, lower power consumption and higher integration can be simultaneously implemented by reducing the operating voltage of the memory cell.
In the conventional stacked gate or split gate memory cell, however, electrons are injected into or extracted from the floating gate electrode as hot electrons or through the FN tunnel current. When employing the silicon oxide film as the insulator film enclosing the floating gate electrode, therefore, it is difficult to reduce the operating voltage of the memory cell beyond the current level while maintaining the thickness of the silicon oxide film at the current level of 8 to 10 nm. In other words, it is difficult to reduce the operating voltage of the memory cell while keeping the life of the conventional stacked gate or split gate memory cell at the current level without changing the structure thereof.
As described above, the feature of the flash memory resides in that the cells sharing a word line are subjected to batch erasing and thereafter subjected to rewriting. Therefore, the cells sharing the word line must be subjected to erasing and writing also when data may not be rewritten. In this case, the data are rewritten in two stages of erasing and writing. Therefore, it is difficult to perform writing on a group of cells forming a block (sector) subjected to batch erasing simultaneously with batch erasing or to perform the so-called overwriting performed in a magnetic disk. Thus, it is difficult to increase the speed for write and erase operations.
SUMMARY OF THE INVENTION
A
Fujiwara Hideaki
Hiroshima Takashi
Nagasawa Hideharu
Sudo Shoji
Armstrong Westerman & Hattori, LLP
Hoang Huan
Sanyo Electric Co,. Ltd.
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