Semiconductor memory and method of controlling the same

Details Semiconductor memory and method of controlling the same Semiconductor memory and method of controlling the same

2005-06-28

2005-06-28

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S185230, C365S145000

Reexamination Certificate

active

06912175

ABSTRACT:
Each of a plurality of memory cells includes one ferroelectric capacitor having one terminal connected to a bit line. A plurality of decoder circuits are arranged on each of the plurality of memory cells, and connected to the other terminal of the ferroelectric capacitor forming the memory cells via a plurality of word lines. These plurality of decoder circuits control the word lines to one of high level, low level, and a floating state, thereby writing data in the memory cells or reading out data from the memory cells.

REFERENCES:
patent: 5487029 (1996-01-01), Kuroda
patent: 5487032 (1996-01-01), Mihara et al.
patent: 6301145 (2001-10-01), Nishihara
patent: 6785155 (2004-08-01), Matsushita
patent: 6788564 (2004-09-01), Hamada
patent: 09116107 (1997-05-01), None

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