Semiconductor memory and method for operating a...

Static information storage and retrieval – Interconnection arrangements

Reexamination Certificate

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C365S205000, C365S190000

Reexamination Certificate

active

07944725

ABSTRACT:
A semiconductor memory has a plurality of read amplifiers to which a pair each of two complementary bit lines is connected, wherein the semiconductor memory includes at least one switching element each for each bit line, by which at least a partial section of the bit line may be electrically decoupled from the read amplifier, and wherein the semiconductor memory controls the first switching element so that the first switching element, when reading out and/or refreshing any memory cell connected to the bit line, temporarily electrically decouples at least the partial section of the bit line from the read amplifier.

REFERENCES:
patent: 4841483 (1989-06-01), Furuyama
patent: 6970389 (2005-11-01), Proell et al.
patent: 2005/0157534 (2005-07-01), Ferrant et al.
patent: 2006/0146593 (2006-07-01), Klehn et al.
patent: 2006/0158924 (2006-07-01), Sekiguchi et al.
patent: 103 01 856 (2004-08-01), None
Min, D-S., et al., “Multiple Twisted Dataline Techniques for Multigigabit DRAM's,” IEEE Journal of Solid-State Circuits, vol. 34, No. 6, Jun. 1999, pp. 856-865, IEEE.
Sekiguchi, T., et al., “A Low-Impedance Open-Bitline Array for Multigigabit DRAM,” IEEE Journal of Solid-State Circuits, vol. 37, No. 4, Apr. 2002, pp. 487-498, IEEE.

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