Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-03-25
2003-12-23
Tran, Mike (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S194000
Reexamination Certificate
active
06667907
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory and a method for applying a voltage to a semiconductor memory device.
In accordance with recent spread of portable equipment and requests for energy saving and reduction of waste, there are increasing demands for a semiconductor device including a nonvolatile memory that is rewritable and capable of storing data even with power off. Examples of the semiconductor nonvolatile memory are a flash memory and a ferroelectric memory, both of which have their own advantages and disadvantages and are characteristic in applied fields of products. For example, a flash memory is suitably applied to attain a large capacity because it has a small memory cell size but it is disadvantageous in a small number of times for rewriting data therein (hereinafter referred to as the rewrite number). On the other hand, a ferroelectric memory is advantageous in a large rewrite number but is not suitably used to attain a large capacity because it has a large memory cell size. An EEPROM is a compromise between a flash memory and a ferroelectric memory in both the memory cell size and the rewrite number.
FIG. 8
shows an exemplified conventional flash memory and is a cross-sectional view of a 1-bit memory cell
80
including two transistors.
The memory cell
80
of
FIG. 8
includes a floating gate
801
, a tunnel oxide film
802
, an interlayer film
803
of ONO or the like, a control gate
804
connected to a control word line, a gate
805
connected to a select word line, a P well
806
, a source
807
connected to a source line, a drain
808
connected to a data line, a thin N-type diffusion layer
809
and an N well
810
.
FIG. 9
shows an exemplified architecture of a circuit used for operating the flash memory
80
of FIG.
8
.
The circuit of
FIG. 9
includes a power circuit
901
for generating predetermined positive and negative voltages, a timing control circuit
902
for controlling timing of applying a voltage, a data line selector/deriver circuit
903
for selecting and driving a data line, a select word line selector/deriver circuit
904
for selecting and driving a select word line, a control word line selector/deriver circuit
905
for selecting and driving a control word line, a source line selector/deriver circuit
906
for selecting and driving a source line, and a well driver circuit
907
for driving a well.
FIG. 10
is a block diagram for explaining the architecture of the timing control circuit
902
of
FIG. 9
, and more particularly, a timing control circuit
902
A used in writing data.
The timing control circuit
902
A of
FIG. 10
includes a pulse generation circuit
1001
for generating a predetermined write pulse from a basic clock, and delay circuits
1002
,
1003
and
1004
for providing predetermined delays respectively to the activations of the aforementioned selector/deriver circuits
907
,
905
and
906
. As shown in
FIG. 10
, the well driver circuit
907
is connected to the timing control circuit
902
A so as to receive a signal from the delay circuit
1002
, the control word line selector/deriver circuit
905
is connected thereto so as to receive a signal from the delay circuit
1003
, and the source line selector/deriver circuit
906
is connected thereto so as to receive a signal from the delay circuit
1004
.
In a data write operation, first, the well driver circuit
907
receives a signal from the delay circuit
1002
and is activated with the predetermined delay from a write pulse so as to apply a predetermined voltage to the P well
806
. The control word line selector/deriver circuit
905
receives a signal from the delay circuit
1003
and is activated with the predetermined delay from the signal so as to apply a predetermined voltage to the control word line. Furthermore, the source line selector/deriver circuit
906
receives a signal from the delay circuit
1004
and is activated with the predetermined delay from the signal so as to apply a predetermined voltage to the source line. In this manner, data is written in the memory cell
80
.
FIG. 11
is a block diagram for explaining the architecture of the timing control circuit
902
of
FIG. 9
, and more particularly, a timing control circuit
902
B used in erasing data.
The timing control circuit
902
B of
FIG. 11
includes a pulse generation circuit
1005
for generating a predetermined erase pulse from a basic clock, and delay circuits
1006
and
1007
for providing predetermined delays respectively to the activations of the aforementioned selector/deriver circuits
907
and
905
. As shown in
FIG. 11
, the well driver circuit
907
is connected to the timing control circuit
902
B so as to receive a signal from the delay circuit
1006
and the control word line selector/deriver circuit
905
is connected thereto so as to receive a signal from the delay circuit
1007
.
In an erase operation, first, the well driver circuit
907
receives a signal from the delay circuit
1006
and is activated with the predetermined delay from an erase pulse so as to apply a predetermined voltage to the P well
806
. The control word line selector/deriver circuit
905
receives a signal from the delay circuit
1007
and is activated with the predetermined delay from the signal so as to apply a predetermined voltage to the control word line. In this manner, data is erased from the memory cell
80
.
FIG. 12
is a diagram for showing operation timings and polarities of the respective signal lines employed in writing data in the memory cell
80
, namely, in injecting electrons into the floating gate
801
.
In the case where electrons are injected into the floating gate
801
via the tunnel oxide film
802
, as shown in
FIG. 12
, negative potential is first applied to the P well
806
at timing
12
a
, positive potential is applied to the control word line at timing
12
b
, and then, negative potential is applied to the source line at timing
12
c
. In this case, the select word line is kept at 0 V.
FIG. 13
is a diagram for showing operation timings and polarities of the respective signal lines employed in erasing data from the memory cell
80
, namely, in extracting electrons from the floating gate
801
.
In the case where electrons are extracted from the floating gate
801
via the tunnel oxide film
802
, as shown in
FIG. 13
, positive potential is first applied to the P well
806
at timing
13
a
, and then negative potential is applied to the control word line at timing
13
b
. In this case, the data line and the source line are opened and the select word line is kept at power potential.
In this manner, the data write operation and the data erase operation are performed.
In the case where data is written as shown in
FIG. 12
, however, a large peak electric field is applied to the tunnel oxide film
802
in a moment when the potential of the source line becomes negative. Therefore, the quality of the tunnel oxide film
802
is degraded, and hence, the rewrite number is reduced and the data storage characteristic is degraded. As a result, the reliability is disadvantageously lowered.
Also, in the case where data is erased as shown in
FIG. 13
, a large peak electric field is applied to the tunnel oxide film
802
in the reverse direction to that applied in the data write operation in a moment when the potential of the control word line becomes negative. Therefore, the quality of the tunnel oxide film
802
is degraded, and hence, the rewrite number is reduced and the data storage characteristic is degraded. As a result, the reliability is disadvantageously lowered.
SUMMARY OF THE INVENTION
An object of the invention is providing a semiconductor memory and a method for applying a voltage to a semiconductor memory device in which reduction of the rewrite number and degradation of the data storage characteristic can be avoided by preventing a peak electric field from being applied to a tunnel oxide film.
In order to overcome the aforementioned disadvantages, the first semiconductor memory of this invention includes a semiconductor me
Chaya Shigeo
Matsuura Masanori
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Tran Mike
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