Static information storage and retrieval – Addressing – Combined random and sequential addressing
Patent
1999-01-19
2000-11-21
Zarabian, A.
Static information storage and retrieval
Addressing
Combined random and sequential addressing
36523003, G11C 800
Patent
active
061512680
ABSTRACT:
A semiconductor memory includes a plurality of memory cells; and an access section for accessing a memory cell, among the plurality of memory cells, corresponding to a row address and a column address. The plurality of memory cells include at least one first memory cell accessible at a first access speed and at least one second memory cell accessible at a second access speed which is higher than the first access speed. The at least one second memory cell is assigned to at least one specified column address.
REFERENCES:
patent: 5663905 (1997-09-01), Matsuo
patent: 5953244 (1999-09-01), Okada
Matsushita Electric - Industrial Co., Ltd.
Zarabian A.
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