Semiconductor memory and layout/circuit information generating a

Details Semiconductor memory and layout/circuit information generating a Semiconductor memory and layout/circuit information generating a

1997-01-15

1998-04-21

Nguyen, Tan T.

Static information storage and retrieval

Read only systems

Semiconductive

365 94, G11C 1600

Patent

active

057425400

ABSTRACT:
NMOS transistors which are provided adjacently to each other in the direction of the formation of bit lines between word lines are paired. The drains of the NMOS transistors are connected in common through a common node to form a memory cell. Between the common node and the bit line is provided a region where a contact is placed. Furthermore, regions where the contact is placed in the respective NMOS transistors are provided on a layout. By these combinations, data are stored.

REFERENCES:
patent: 4773047 (1988-09-01), Uchino et al.
patent: 5517061 (1996-05-01), Azmanov

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