Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-03-15
2003-06-03
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180
Reexamination Certificate
active
06574149
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor memory and its usage and it is more useful in recording 2-bit information in one memory cell in a nonvolatile semiconductor memory.
BACKGROUND ART
In recent years, the nonvolatile semiconductor memory capable of recording 2-bit information in one memory cell by arranging the carrier injection position have been studied and developed. This nonvolatile semiconductor memory is so characterized that carriers are trapped in a gate insulation film formed below the gate. The direction of a voltage applied between a source and a drain is reversed depending upon a write or read mode of information. Electrons are therefore independently captured, in the gate insulation film, at positions corresponding to the two ends of a channel area. Accordingly, the 2-bit information can be recorded depending on whether electrons are captured or not at the two ends.
For example, International Patent Laid-Open No. WO 99/07000 discloses a nonvolatile semiconductor memory having this structure. The structure of a nonvolatile semiconductor memory and the data write/erase processing in the nonvolatile semiconductor memory taught in this document will be briefly described with reference to
FIGS. 5A and 5D
.
As shown in
FIGS. 5A
to
5
D, a nonvolatile semiconductor memory
100
comprises first and second diffused layers
102
and
103
functioning as a source/drain formed in the surface area of a p-type silicon substrate
101
, a gate insulation film
104
including a carrier trap area
104
a
formed on the p-type silicon substrate
101
almost between the first and second diffused layers
102
and
103
, and a gate electrode
105
formed on the gate insulation film
104
. The carrier trap area
104
a
includes a silicon nitride film or the like, and exhibits a higher carrier trap characteristic than that of the other areas within the gate insulation film
104
.
In this nonvolatile semiconductor memory
100
, electrons are captured independently at areas
106
and
107
which correspond to two ends of the channel area in the gate insulation film
104
, so that a 2-bit information can be finally recorded.
FIG. 5A
shows a state wherein the electrons are not captured yet in the gate insulation film
104
. This state of the memory cell (threshold voltage: V
th
) defines a “Erase State”. When 0 (zero) V to the first diffused layer
102
, nearly 5 V to the diffused second layer, and 10 V to the gate electrode
105
in this memory cell are applied respectively, hot electrons are generated near the second diffused layer
103
, the electrons are captured in the area
106
in the gate insulation film
104
near the second diffused layer
103
, and the memory cell shift to a programmed state.
To capture electrons in the other area
107
, the programming voltages applied to the first and second diffused layers
102
and
103
are switched; or 5 V to the first diffused layer
102
, 0 (zero) V to the second diffused layer
103
, and 10 V to the gate electrode
105
are applied respectively. Then, the electrons are captured in both areas
106
and
107
, as shown in FIG.
5
B.
To electrically return the state (programmed state) wherein electrons are locally captured in the areas
106
and
107
, as shown in
FIG. 5B
, to the erase state shown in
FIG. 5A
, +5 V to the first and second diffused layers
102
and
103
and −5 V to the gate electrode
105
are applied, respectively. In this case, electrons captured in the gate insulation film
104
near the first and second diffused layers
102
and
103
are neutralized by hot holes locally generated near the first and second diffused layers
102
and
103
. Thus, the stored data in the programmed state can be erased.
However, if the electrons captured in the gate insulation film
104
diffusely exist in the lateral direction (along the first and second diffused layers
102
and
103
in
FIG. 5C
) due to repulsion against each other, disturbance in the read mode, as shown in
FIG. 5C
, it is difficult to completely erase the electrons in all the area. Especially when the write and read modes are repeated, the electrons remain at the center of the channel area in the gate insulation film
104
and they are gradually accumulated.
In the erase processing under the above-described voltage conditions, only electrons captured near the first and second diffused layers
102
and
103
may be neutralized, because the captured electrons are neutralized by injecting into the gate insulation film
104
hot holes generated near the first and second diffused layers
102
and
103
. Therefore, in the erase processing under the above-described voltage conditions, the electrons remained near the center of the channel cannot be neutralized nor erased.
The electrons, which cannot be erased and remained near the center of the channel in the gate insulation film
104
, causes an increase of the threshold voltage (V
th
) for the memory cell, so the memory cell state shown in
FIG. 5B
cannot be discriminated against that shown in FIG.
5
D. In the memory cell state shown in
FIG. 5D
, the capture state of the electrons in the area
106
or
107
can not be confirmed to thereby lower the writing reliability.
The present invention has been made to overcome the conventional drawbacks, and has as its object to provide a semiconductor memory capable of reliably erasing captured electrons even when the electrons captured in a gate insulation film of a memory cell diffuse laterally, and its usage based on a characteristic erase algorithm for erasing captured electrons to thereby increase the data write/erase reliability.
SUMMARY OF THE INVENTION
According to the present invention, there is provided a semiconductor memory which has a pair of impurity-diffused layers formed in a surface area of a semiconductor substrate, and a gate electrode formed on a gate insulation film on the semiconductor substrate between the pair of impurity-diffused layers, to thereby traps carriers at different positions in the gate insulation film by applying a predetermined voltage to the gate electrode, and wherein a tunnel current is supplied between the semiconductor substrate and the gate electrode by applying a first voltage to the semiconductor substrate including the pair of impurity-diffused layers and applying a second voltage to the gate electrode, and the tunnel current erases the carriers trapped in the gate insulation film.
According to the present invention, there is provided a usage of a semiconductor memory which has a pair of impurity-diffused layers formed in a surface area of a semiconductor substrate, and a gate electrode formed on a gate insulation film on the semiconductor substrate between the pair of impurity-diffused layers, to thereby trap carriers at different positions in the gate insulation film by applying a predetermined voltage to the gate electrode, comprising the steps of: supplying a tunnel current between the semiconductor substrate and the gate electrode by applying a first voltage to the semiconductor substrate including the pair of impurity-diffused layers and applying a second voltage to the gate electrode, and erasing the carriers trapped in the gate insulation film by the tunnel current.
The present invention is realized by the above technique. By supplying a tunnel current between the semiconductor substrate and the gate electrode, electrons in the entire area of the gate insulation film can be reliably erased regardless of the position where electrons are captured in the gate insulation film. Hence, electrons remaining near the center of the channel area, which are particularly difficult to erase, can be reliably erased.
The present invention can surely erase electrons without leaving them near the center of the channel area in a semiconductor memory in which electrons are captured in an insulation film having a carrier trap area. The present invention can therefore provide a semiconductor memory which increases the reliability by reliably erasing electrons.
REFERENCES:
patent: 5414665 (1995-05-01), K
Einaga Yuichi
Itano Kiyoshi
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