Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2002-03-21
2003-09-09
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S218000, C327S208000
Reexamination Certificate
active
06617902
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-095024, filed Mar. 29, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor holding device capable of realizing low power consumption in a clock system circuit, such as a latch circuit and a flip-flop circuit, and an integrated circuit including the semiconductor holding device.
2. Description of the Related Art
In recent years, low power consumption techniques have become important due to the demands of portable devices, in particular, and it becomes important to suppress the power consumption without decreasing the processing speed. The power consumption of the clock system circuit of a semiconductor integrated circuit accounts for a high percentage of the total power consumed by an integrated circuit. This may be as large as several tens of percent depending upon products. This is substantially equal to the power consumption of the parts other than the clock system circuit. The possible cause that the clock circuit occupies large portion of the power consumption of the semiconductor integrated circuit is based on that transition probability of a part other than the clock system circuit is about 30% generally whereas the transition probability of the clock system circuit is 100%. Furthermore, nearly 90% of the power consumption of this clock system circuit are occupied by the semiconductor holding device of the last stage (latch circuit or flip-flop circuit), a clock system circuit driving the memory and holding device, and wiring connecting between the memory and holding device and the clock system circuit. It contributes to low power consumption of the whole integrated circuit greatly and is very important to reduce the power consumption in the last stage of the clock system circuit from the above reason.
It is an object of the present invention to provide a semiconductor holding circuit which is operable with a reduced clock-swing signal.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the invention, there is provided a semiconductor holding device comprising:
a first transistor circuit including a P type first transistor connected to a first power source, an N type second transistor connected to the first transistor and an N type third transistor connected to the second transistor and a second power source; a second transistor circuit including a P type fourth transistor connected to the first power source, an N type fifth transistor connected to the fourth transistor and an N type sixth transistor connected between the fifth transistor and the second power source; and a clock generator which generates a small swing clock to be supplied to gates of the N type third and sixth transistors, an input signal being supplied to gates of the P type first transistor and the N type second transistor, a node of the first and second transistors being connected to gates of the fourth and fifth transistors, and a node of the fourth and fifth transistors serving as an output node.
REFERENCES:
patent: 5619157 (1997-04-01), Kumata et al.
patent: 5789956 (1998-08-01), Mahant-Shetti et al.
patent: 6157361 (2000-12-01), Kubota et al.
patent: 6304123 (2001-10-01), Bosshart
patent: 6437624 (2002-08-01), Kojima et al.
Hiroshi et al., “A Reduced Clock-Swing Flip-Flop (RCSDFF) for 63% Power Reduction”, IEEE Journal of Solid-State Circuits, vol. 33, No. 5, May 1998, pp. 807-811.*
Nikola Nedovic, et al., “Hybrid Latch Flip-Flop with Improved Power Efficiency”, IEEE, 13thIntegrated Circuits and System Design, 2000, pp. 211-215.
Hirotsugu Kojima, et al., “Half-Swing Clocking Scheme for 75% Power Saving in Clocking Circuitry”, IEEE Journal of Solid-State Circuits, vol. 30, No. 4, Apr. 1995, pp. 432-435.
Young-Su Kwon, et al., “A New Single-Clock Flip-Flop for Half-Swing Clocking”, IEICE Trans. Fundamentals, vol. E82-A, No. 11, Nov. 1999, pp. 2521-2526.
Daniel W. Dobberpuhl, et al., “A 200-MHz 64-b Dual-Issue CMOS Microprocessor”, IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1555-1567.
Hamid Partovi, et al., “Flow-Through Latch and Edge-Triggered Flip-Flop Hybrid Elements”, IEEE, ISSCC Digest of Technical Papers, Feb. 1996, pp. 138-139.
Hiroshi Kawaguchi, et al., “A Reduced Clock-Swing Flip-Flop (RCSFF) for 63% Power Reduction”, IEEE Journal of Solid-State Circuits, vol. 33, No. 5, May 1998, pp. 807-811.
Jin-Cheon Kim, et al., “A Low-Power Half-Swing Clocking Scheme for Flip-Flop with Complementary Gate and Source Drive”, IEICE Trans. Electron., vol. E82-C, No. 9, Sep. 1999, pp. 1777-1779.
Fujii Hiroshige
Tokumasu Motoki
Cunningham Terry D.
Nguyen Long
LandOfFree
Semiconductor memory and holding device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory and holding device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory and holding device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3028570