Semiconductor memory and control method thereof allowing...

Details Semiconductor memory and control method thereof allowing... Semiconductor memory and control method thereof allowing...

2006-12-26

2006-12-26

Tran, M. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185220

Reexamination Certificate

active

07154787

ABSTRACT:
In write/erase verity operations of a memory transistor in a semiconductor memory, control of the semiconductor memory follows the following process. One main bit line is applied to be operative on the select side and another main bit line is applied to be operative on the reference side. On the select side, a sub bit line select transistor is turned on to select a sub bit line having connection to the memory transistor as a target for write/erase verify operations. The target memory transistor is turned on while the other memory transistors connected to the same sub bit line are turned off. On the reference side, a sub bit line select transistor is turned off to bring a sub bit line to a non-selected state.

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