Semiconductor memory address buffer having power down mode

Details Semiconductor memory address buffer having power down mode Semiconductor memory address buffer having power down mode

1981-08-21

1983-05-24

Stellar, George G.

Static information storage and retrieval

Powering

Conservation of power

365230, G11C 800

Patent

active

043853692

ABSTRACT:
A semiconductor memory address buffer (10) includes a plurality of serially connected inverter amplifier stages (76, 78, 80, and 82). An output stage (84) is connected to the last two inverter amplifier stages (80, 82). In the active mode of operation circuit (10) functions as a driver which receives an input address signal (A) and produces complementary output address signals (A, A). In a power down mode a group of transistors (18, 20 and 22) are turned off to deactive corresponding stages (76, 78 and 82) to terminate power consumption by these stages. A transistor (36) is activated to drive the input node (38) of a selected stage (80) to turn off a transistor (48) and essentially terminate power consumption by the selected stage (80). The output stage (84) receives differential inputs and functions in a push-pull configuration to produce the complementary output address signals (A, A). In the power down mode the buffer (10) has essentially zero power consumption while producing predetermined state complementary output signals (A, A).

REFERENCES:
patent: 4159540 (1979-06-01), Smith et al.
patent: 4185321 (1980-01-01), Iwahashi et al.

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