Semiconductor memory

Details Semiconductor memory Semiconductor memory

1996-10-03

1999-07-20

Zarabian, A.

Static information storage and retrieval

Addressing

Plural blocks or banks

365 51, G11C 800

Patent

active

059264314

ABSTRACT:
Banks are arranged on a memory chip, forming a matrix. A data input/output circuit is provided at one side of the memory chip. A data bus is provided among the banks and connected to the data input/output circuit. Each bank has a plurality of memory cell arrays a cell-array controller, a row decoder, column decoders, and a DQ buffer. The cell-array controller and the row decoder oppose each other. The column decoders oppose the DQ buffer. Local DQ lines are provided between the memory cell arrays, and global DQ liens extend over the memory cell arrays. The local DQ lines extend at right angles to the global DQ lines.

REFERENCES:
patent: 5502675 (1996-03-01), Kohno
patent: 5517456 (1996-05-01), Chishiki
patent: 5586078 (1996-12-01), Takase
patent: 5598374 (1997-01-01), Rao
patent: 5706244 (1998-01-01), Shimizu

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