Semiconductor memory

Static information storage and retrieval – Addressing – Sync/clocking

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Details

36518911, G11C 800

Patent

active

056549350

ABSTRACT:
A semiconductor memory includes a plurality of memory cells aligned in rows and columns, a plurality of bit lines respectively connected to the columns of the plurality of memory cells, a plurality of switch circuits each having one end connected to a corresponding one of the plurality of bit lines, the plurality of switch circuits being selectively turned on in accordance with a column address signal input from an outside to identify each of the columns, a data line to which the other end of each of the plurality of switch circuits is commonly connected, a pulse generation circuit for detecting a change in level of the column address signal with respect to first and second circuit thresholds different from each other to generate a pulse signal, the first circuit threshold being used for detecting a change in address signal from one level to the other level, and the second circuit threshold being used for detecting a change in address signal from the other level to one level, and a data detection circuit, connected to the data line and controlled by the pulse signal generated in accordance with the pulse generation circuits, for amplifying a potential of the data line to detect data.

REFERENCES:
patent: 5047984 (1991-09-01), Monden

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