Static information storage and retrieval – Addressing – Plural blocks or banks
Patent
1990-02-14
1991-01-08
Popek, Joseph A.
Static information storage and retrieval
Addressing
Plural blocks or banks
36523008, G11C 700
Patent
active
049842129
ABSTRACT:
An electrically programmable read only memory is equipped with latch circuits for sequentially introducing series signals which are fed through external terminals. The converter includes sequentially operated switch elements and latch circuits in order to convert the series signals into parallel signals. The thus converted parallel signals are written simultaneously in a memory array via address decoder operated selection switch elements. According to this method, the writing operations into the memory array can be conducted at a high speed even when one writing operation is relatively long as a result of the parallel signal action.
REFERENCES:
patent: 4130900 (1978-12-01), Watanabe
patent: 4279024 (1981-07-01), Schrenk
patent: 4691298 (1987-09-01), Fukuda et al.
patent: 4788665 (1988-11-01), Fukuda et al.
patent: 4905195 (1990-02-01), Fukuda et al.
Fukuda Minoru
Kihara Toshimasa
Sugiura June
Takahashi Hideaki
Tsuchiya Fumio
Hitachi , Ltd.
Popek Joseph A.
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