Static information storage and retrieval – Addressing – Plural blocks or banks
Patent
1999-11-09
2000-08-22
Nguyen, Tan T.
Static information storage and retrieval
Addressing
Plural blocks or banks
365236, 36523004, G11C 800
Patent
active
061082651
ABSTRACT:
A semiconductor memory comprises two banks each including a number of memory cells arranged in the form of a matrix having a plurality of rows and a plurality of columns, each of the banks having a plurality of data input/output lines extending in a column direction, so that the data input/output lines can sequentially accessed at a designated row address. The semiconductor memory also comprises a bank judgment circuit receiving an address signal for discriminating a first bank to be firstly accessed of the at least two banks, a row address counter for designating a row address at which the first bank is continuously accessed, and a bank switch circuit for switching access to a second bank to continuously access to the second bank after an access to the most significant column address in the first bank has been finished. Thus, a reading or writing operation is continuously executed for the first bank and the second bank by alternately accessing the first bank and the second bank.
REFERENCES:
patent: 5864505 (1999-01-01), Higuchi
patent: 6011745 (2000-01-01), Okamura
NEC Corporation
Nguyen Tan T.
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