Semiconductor memory

Details Semiconductor memory Semiconductor memory

1990-08-13

1991-03-12

James, Andrew J.

357 51, 357 55, H01L 2968

Patent

active

049996894

ABSTRACT:
A semiconductor memory having a plurality of memory cells each including a single capacitor and a single transistor for storing one bit are formed on a semiconductor substrate. Each terminal of the respective transistors of the memory cells are commonly connected to a common wiring portion, and the capacitor of each memory cell is disposed in a trench which is formed by forming a groove-like shape along the outer periphery of the semiconductor substrate for one or two adjacent transistors. The capacitor includes a first insulating film disposed over the inner wall surface of the trench, a first electrode formed entirely or partially on the surface of the first insulating film for being supplied with a predetermined voltage, a second insulating film disposed entirely over the surface of the first electrode, and a second electrode disposed on the second insulating film in an area corresponding to the inner sidewall surface of the trench and connected to the other terminal of the transistor.

REFERENCES:
patent: 4801989 (1989-01-01), Taguchi
Chang et al., "Fabrication of V-MOS or U-MOS Random-Access Memory Cells with a Self-Aligned Word Line", Dec. 1979, IBM Technical Disclosure Bulletin, vol. 22, No. 7, pp. 2768-2771.
Richardson et al., "A Trench Transistor Cross-Point Dram Cell"; 1985, IEDM, p. 714.
M. Sakamoto et al., "Buried Storage Electrode (BSE) Cell for Megabit Drams"; 1985, IEDM, p. 710.
S. Nakajima et al., "An Isolation-Merged Vertical Capacitor Cell for Large Capacity Dram", 1985, IEDM; p. 240.
M. Wada et al., "A Folded Capacitor Cell (F.C.C.) for Future Megabit Drams", 1984, IEDM, p. 244.
M. Nagatomo et al., "A High Density 4M Dram Process Using Folded Bitline Adaptive Side-Wall Isolated Capacitor (FASIC) Cell"; 1986, IEDM, p. 144.
M. Taguchi et al., "Dielectrically Encapsulated Trench Capacitor Cell", 1986, IEDM, p. 136.

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