Semiconductor memory

Details Semiconductor memory Semiconductor memory

1988-07-01

1990-02-06

Popek, Joseph A.

Static information storage and retrieval

Addressing

Combined random and sequential addressing

36523002, G11C 800

Patent

active

048993123

ABSTRACT:
An improved DRAM which includes a plurality of main amplifiers for amplifying and storing signals read out to a plurality of common data lines in accordance with an internal address signal, a main amplifier control circuit for outputting the outputs of the main amplifiers sequentially in synchronism with changes in a column address strobe signal and an address counter for performing an addressing operation midway in the sequential reading operations of the plural main amplifiers. The present invention also includes a column selecting circuit for switching column switches in accordance with the address counter to cause data to be read out continuously at a high speed by extending a nibble mode.

REFERENCES:
patent: 4567579 (1986-01-01), Patel et al.
patent: 4618947 (1986-10-01), Tran et al.
patent: 4758995 (1988-07-01), Sato

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