Semiconductor memory

Details Semiconductor memory Semiconductor memory

2006-12-19

2006-12-19

Tran, Michael (Department: 2827)

Static information storage and retrieval

Interconnection arrangements

C365S230030

Reexamination Certificate

active

07151684

ABSTRACT:
The present invention avoids generation of voids in regions in which bit line contacts CB are to be formed in a row. A semiconductor memory, mounted on a semiconductor chip, includes bit lines BL and a source line SL and word lines WL orthogonal to the bit lines. The device further includes: bit line side select gate lines SGD and source line side select gate lines SGS that are aligned parallel to the word lines and adjacent to both ends thereof aligned along the bit line length; memory cell transistors MT that are arranged at the intersections of the bit lines and the word lines; select gate transistors ST that are arranged at the intersections of the bit lines and the select gate lines; bit line contacts CB that are arranged along the word line length between the bit line side select gate lines; and source line contacts CS that are arranged along the word line length between the source line side select gate lines; wherein interval L1between the bit line side select gate lines is greater than interval L2between the source line side select gate lines.

REFERENCES:
patent: 7023049 (2006-04-01), Takebuchi et al.
patent: 2004/0212008 (2004-10-01), Hasegawa
patent: 2005/0029573 (2005-02-01), Sato et al.
patent: 2005/0254302 (2005-11-01), Noguchi
patent: 3-283662 (1991-12-01), None
patent: 2001-196482 (2001-07-01), None
patent: 2002-110791 (2002-04-01), None

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