Semiconductor memory

Details Semiconductor memory Semiconductor memory

2005-08-02

2005-08-02

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Powering

Data preservation

C365S189050, C365S226000

Reexamination Certificate

active

06925027

ABSTRACT:
A semiconductor memory with a memory core for dynamically holding data in which a data collision at the time of the semiconductor memory making the transition from a standby state to a nonstandby state is prevented. A first buffer circuit inputs an enable signal for controlling a standby state or a nonstandby state. A second buffer circuit outputs a predetermined logic signal or a read/write signal for controlling the reading of data from or the writing of data to the memory core in accordance with the enable signal. A third buffer circuit outputs an inverted signal obtained by inverting the logic signal or the read/write signal in accordance with the enable signal. A control circuit controls the reading or writing of the data by the read/write signal outputted from the second buffer circuit. A data output control circuit controls the inputting of the data from or the outputting of the data to the outside by the inverted signal or the read/write signal outputted from the third buffer circuit.

REFERENCES:
patent: 6049488 (2000-04-01), Sawada
patent: 6101144 (2000-08-01), Jo
patent: 6552957 (2003-04-01), Yagishita
patent: 6560158 (2003-05-01), Choi et al.
patent: 6870383 (2005-03-01), Kitazaki
patent: 11-317076 (1999-11-01), None

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