Semiconductor memory

Static information storage and retrieval – Associative memories – Ferroelectric cell

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S233100

Reexamination Certificate

active

06894912

ABSTRACT:
A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.

REFERENCES:
patent: 4928260 (1990-05-01), Chuang et al.
patent: 4959811 (1990-09-01), Szczepanek
patent: 5050126 (1991-09-01), Tanaka et al.
patent: 5371711 (1994-12-01), Nakayama
patent: 5592407 (1997-01-01), Konishi et al.
patent: 6075735 (2000-06-01), Sugibayashi
patent: 6400626 (2002-06-01), Williams et al.
patent: 6414893 (2002-07-01), Miyamoto
patent: 6480406 (2002-11-01), Jin et al.
patent: 6560670 (2003-05-01), Ichiriu
patent: 6597594 (2003-07-01), Waller
patent: 11-110967 (1997-10-01), None
patent: 2002-93158 (2000-09-01), None

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3384975

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.