Semiconductor memory

Details Semiconductor memory Semiconductor memory

1995-06-02

1999-02-23

Zarabian, A.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518911, G11C 800

Patent

active

058751483

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

The present invention relates to a semiconductor memory such as a dynamic random access memory (hereafter referred to as a "DRAM").


BACKGROUND ART

The following reference describes a conventional DRAM:
Reference: 1992 Symposium on VLSI Circuits Digest of Technical Papers IEEE "A Boosted Dual Word-Line Decoding Scheme for 256 Mb DRAMs" P. 112-113 (K. Noda et al.)
The memory cell area of the conventional DRAM described in this reference is divided by a plurality of memory arrays. This DRAM is provided with a plurality of bit line couples and a plurality of word lines which are intersection-arranged on respective memory cell arrays. Each memory cell array is provided with word line drive circuits for driving the word lines. These word line drive circuits are provided along a plurality of memory arrays. In addition, this DRAM has sense amplifiers connected to a plurality of bit line couples. These sense amplifiers are provided in parallel with the word lines. Line decoders are provided along the word line drive circuits near this memory cell area. These line decoders are used to select the main word lines. A plurality of drive signal generating circuits are arranged concentrated at one-side ends of the word line drive circuits near the memory cell area. These drive signal generating circuits are for supplying the drive signals to a plurality of word line drive circuits.
In this DRAM, a main word line is selected by boosting one of the main word lines to a voltage VBOOT, which is higher than the power supply voltage VCC, by the line decoder. Thus the word line drive circuits connected to the selected main word line become ready to operate. A drive signal generating circuit operates in response to a specified address signal to supply a drive signal to the specified word line drive circuit. The word line drive circuits to which the drive signal is supplied boost the specified word lines connected thereto to the voltage VBOOT and the data stored in the memory cells connected to these word lines is outputted to the bit line couples.
Lately, semiconductor memories such as the DRAM have been demanded to provide higher operating speeds along with the increased storage capacities.
An object of the present invention is to provide a semiconductor memory which has implements high speed operation.


SUMMARY OF THE INVENTION

A semiconductor memory comprising semiconductors as a first aspect of the present invention made to fulfill the above-described object comprises a plurality of bit lines; a plurality of word lines arranged intersecting these bit lines; first and second memory cell arrays having a plurality of memory cells connected to the bit lines and the word lines and arranged at the intersections of these bit lines and word lines; a first drive circuit arranged adjacent to the first memory cell array to drive part of the word lines; a second drive circuit arranged adjacent to the second memory cell array to drive the other part of the word lines; a third drive circuit for driving those word lines arranged adjacent to the word lines to be driven by the first and second drive circuits; a main word line which connects the first, second and third drive circuits to each other, a line control circuit for selecting a bit line according to address information to be entered, and a decoding circuit for decoding the address information and driving the main word lines, wherein the wiring of the word lines is formed by a gate wiring layer of transistors and a first metal wiring layer connected to this gate wiring layer, the wiring of the line control circuit is formed by a second metal wiring layer which is arranged on the first metal wiring layer and intersects the word lines, and the wiring of the main word lines is formed by a third metal wiring layer which is arranged on the second metal wiring layer parallel to the word lines of the first memory cell array and the word lines of the second memory cell array.
With the above, the improvement for higher operation speed is implemented.
To achieve the

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Symposium on VLSI Circuits Digest of Technical Papers IEEE (1992) "A Boosted Dual Word-Line Decoding Scheme for 256 mb DRAMs", pp. 112-113, K. Noda et al.

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