Semiconductor memory

Details Semiconductor memory Semiconductor memory

2003-03-19

2004-05-11

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S230030, C365S189070

Reexamination Certificate

active

06735101

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based on, and claims priority to, Japanese Application No. 2002-105898, filed Apr. 9, 2002, in Japan, and which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a semiconductor memory and, more particularly, to a semiconductor memory, such as a content addressable memory (CAM), which outputs an address where data to be retrieved is stored.
(2) Description of the Related Art
Retrieval operation for retrieving an address where input data (data to be retrieved) is stored is the characteristic operation of CAMs. Data to be retrieved input from the outside and data in a cell are compared by this retrieval operation. Cells in a CAM which enable this operation have a structure shown in FIG.
19
.
As shown in
FIG. 19
, one cell included in a CAM includes metal oxide semiconductor (MOS) transistors (hereinafter referred to simply as transistors)
1
a
,
2
a
,
3
a
,
6
a
,
1
b
,
2
b
,
5
b
, and
6
b
and inverters
3
a
,
4
a
,
3
b
, and
4
b.
The transistors
1
a
and
2
a
and the inverters
3
a
and
4
a
store an ordinary bit. The transistors
1
b
and
2
b
and the inverters
3
b
and
4
b
store an auxiliary bit.
The transistors
5
a
,
5
b
,
6
a
, and
6
b
judge whether or not signals applied to retrieval data lines SD and XSD match data which has been stored in the cell.
Signal lines XBL
0
, BL
0
, XBL
1
, and BL
1
are used to write and read data.
Data to be retrieved is input to the retrieval data lines SD and XSD. A word line WL is a selection control signal line located in the direction of a row of cells. A match line ML is a match detection signal line for transmitting the result of matching located in the direction of a row of cells.
Now, operation in the above conventional CAM will be described.
FIG. 20
is a truth table showing the state of the cell shown in FIG.
19
. As shown in
FIG. 20
, the cell shown in
FIG. 19
stores the logical value “1,” “0,” or “X (undefined).” To be concrete, assuming that the input sides of the transistors
6
a
and
6
b
are N
1
and N
2
respectively, the state in which N
1
is “L” and N
2
is “H” corresponds to “1,” the state in which N
1
is “H” and N
2
is “L” corresponds to “0,” and the state in which N
1
is “L” and N
2
is “L” corresponds to “X.”
For example, if the logical value “1” has been stored and “0” is input as a value to be retrieved, that is to say, if the retrieval data line SD is put into the “H” state and the retrieval data line XSD is put into the “L” state, then the transistors
5
a
and
6
a
go into the ON state and the transistors
5
b
and
6
b
go into the OFF state. As a result, the match line ML is grounded by the transistors
5
a
and
6
a
and goes into the “L” state. A mismatch therefore will be detected.
On the other hand, if the logical value “1” has been stored and “1” is input as a value to be retrieved, that is to say, if the retrieval data line SD is put into the “L” state and the retrieval data line XSD is put into the “H” state, then the transistors
5
b
and
6
a
go into the ON state and the transistors
5
a
and
6
b
go into the OFF state. As a result, the match line ML is not grounded and remains in the “H” state. A match therefore will be detected.
The above is basic operation in one memory cell.
Now, a content addressable memory word (hereinafter referred to simply as a memory word) in which a plurality of memory cells, each of which is the same as the one shown in
FIG. 19
, are connected will be described.
FIG. 21
is a view showing the structure of a memory word. As shown in
FIG. 21
, a memory word includes a plurality of memory cells connected, each of which is the same as the one shown in FIG.
19
. In this example, only two memory cells
10
and
11
are shown, but in reality more memory cells are connected.
The memory cells
10
and
11
are wired-OR-connected to a match line ML. If data to be retrieved input to the memory cells
10
and
11
via retrieval data lines SD
1
and XSD
1
and retrieval data lines SD
2
and XSD
2
, respectively, does not match data which has been stored in them, then the match line ML is grounded.
The memory cell
10
includes storage sections
10
a
and
10
b
and transistors
10
c
through
10
f
. Each of the storage sections
10
a
and
10
b
corresponds to the two transistors and two inverters shown in FIG.
19
.
The memory cell
11
also includes storage sections
11
a
and
11
b
and transistors
11
c
through
11
f
. Each of the storage sections
11
a
and
11
b
also corresponds to the two transistors and two inverters shown in FIG.
19
.
An inverter
13
inverts a signal applied to the match line ML and outputs it as an output signal OUT.
When a pre-charge line MLEZ goes into the “L” state, a transistor
12
pre-charges the match line ML.
Now, operation in the above example will be described.
FIG. 22
is a timing chart for describing operation in the above example.
At time T
0
the circuit is in a standby state. The pre-charge line MLEZ is in the “L” state (see FIG.
22
(A)), so the match line ML is in a pre-charged state.
At time T
1
the pre-charge line MLEZ goes into the “H” state (see FIG.
22
(A)). Then the transistor
12
goes into the OFF state and the match line ML is released from the pre-charged state.
At time T
2
the data “0” to be retrieved is input. Then the retrieval data line SD
1
goes into the “H” state (see FIG.
22
(B)) and the retrieval data line XSD
1
goes into the “L” state (see FIG.
22
(C)).
Assuming that the data “1” has been stored in the memory cell
10
at this time, output from the storage section
10
a
goes into the “H” state and output from the storage section
10
b
goes into the “L” state.
As a result, both the transistors
10
c
and
10
d
go into the ON state. Therefore, the match line ML is grounded and goes into the “L” state (see FIG.
22
(D)).
The match line ML goes into the “L” state and at time T
3
output from the inverter
13
goes into the “H” state. This indicates that a mismatch has occurred in the memory word.
At time T
4
the pre-charge line MLEZ goes into the “L” state and the match line ML is charged and goes into the “H” state. As a result, one cycle ends.
By the way, the above retrieval operation is performed on the entire chip. For example, if a memory word includes N cells and there are M memory words in the entire device, then N×M memory cells will operate at the same time.
Operating a memory cell involves charging and discharging the match line ML and driving the retrieval data line SD. Therefore, a large amount of power will be consumed to drive these N×M memory cells.
SUMMARY OF THE INVENTION
The present invention was made under the background circumstances as described above. An object of the present invention is to provide a semiconductor memory which consumes only a small amount of power at retrieval operation time.
In order to achieve the above object, a semiconductor memory comprising a plurality of content addressable memory words, a plurality of memory cells connected to each content addressable memory word, memory word blocks each including N content addressable memory words, a storage circuit which has stored a plurality of patterns of information indicative of whether to activate each memory word block, an activation circuit for activating each content addressable memory word block according to a specified pattern in the case of specification information for specifying a predetermined pattern from among the plurality of patterns of information which has been stored in the storage circuit being input, and a specification circuit for specifying a content addressable memory word which has stored data corresponding to data to be retrieved from among a group of content addressable memory words activated by the activation circuit in the case of the data to be retrieved being input is provided.
The above and other objects, features and advantages of the present invention will become apparent from the following description when taken in c

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