Semiconductor memory

Details Semiconductor memory Semiconductor memory

2003-11-19

2004-09-21

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S203000, C711S108000

Reexamination Certificate

active

06795325

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory including CAM (Content Addressable Memory) cells.
2. Description of Related Art
Recently, a semiconductor memory composed of T-CAM (Ternary-Content Addressable Memory) cells has come to be used in a search system of a network address path. A configuration of a T-CAM cell is shown in FIG. 12 of a Relevant Reference 1, for example. It includes two memory cells with a RAM structure for expressing ternary data “0”, “1” and “X (Don't care)”. Each memory cell is connected to a pair of search lines for searching for binary data “0” and “1”. In addition, each CAM cell is connected to a match line for indicating a match result between the search data on the search lines and the memory data in the memory cells.
Next, the outline of the search operation will be described.
First, the match line is charged to a high level, and one of the search data “0” and “1” is set on the search lines. Subsequently, matching is carried out between the search data on the search lines and the memory data in the memory cells (one of the values “0”, “1” and “X”). If the two data match, the match line is maintained at the high level, and a decision is made as “match” as the search result. In other words, a decision is made that the search data is present at the address having that memory data. On the contrary, if the two data do not match, the match line is discharged to a low level, and a decision is made that the search result is “mismatch”. A series of the search operation is repeated in search cycles synchronizing to an external clock.
Relevant Reference 1: Japanese patent application laid-open No. 2002-237190.
The conventional semiconductor memory composed of the CAM cells has a problem of consuming very large power in the search operation because it activates all the search lines at every search cycle.
The problem will be described in more detail by way of example.
FIG. 9
is a timing chart illustrating a search operation of a semiconductor memory composed of the conventional T-CAM cells. In
FIG. 9
, “CLK” designates the external clock supplied from the outside. The search operation is carried out in search cycles synchronized to the external clock. In
FIG. 9
, “RETRIEVAL SEARCH DATA” designates the search data that is being searched for. In addition, “AMP”, “OUTPUT LINE” and “PRECHARGE” designate the operation of an amplifier for amplifying the output from the match line constituting a search result, the output value of the amplifier, and the state of the match line precharged to the high level before the search operation, respectively.
As illustrated in
FIG. 9
, the search lines repeat an inversion to either all “0” or all “1” at every search cycle in response to the search data supplied from the outside in the search operation. When the data values of all the search lines are inverted at every search cycle, the power consumption for executing a search instruction becomes very large. For example, a 9 M-bit class T-CAM consumes power of about 10 watts for a 100 MHz search cycle.
SUMMARY OF THE INVENTION
The present invention is implemented to solve the foregoing problem. It is therefore an object of the present invention to provide a semiconductor memory capable of reducing the power consumption by decreasing the activation frequency of the search lines in the search operation.
According to a first aspect of the present invention, there is provided a semiconductor memory comprising: a memory cell block that consists of L memory cells each for storing 1-bit digital value, where L is an integer equal to mth power of 2, and stores memory data expressing a combination of digital values stored in the individual memory cells in terms of an M-bit digital value, where M is a positive integer equal to or greater than two; search lines on which 1-bit digital values are set to be matched with the digital values stored in the memory cells; a search data setting section for setting search data expressing the combination of the L-bit digital values in terms of the M-bit digital value by setting the 1-bit digital values on the L search lines; a match section for making a match/mismatch decision between the memory data and the search data by matching the digital value stored in the memory cells constituting the memory cell block with the digital value set on the search lines connected to the memory cells; and an output section for outputting a decision result of the match section. Thus, it can reduce the activation frequency of the search lines during the search operation, thereby offering an advantage of being able to reduce the power consumption in the search operation.


REFERENCES:
patent: 5949696 (1999-09-01), Threewitt
patent: 6320777 (2001-11-01), Lines et al.
patent: 6674660 (2004-01-01), Shau
patent: 6697277 (2004-02-01), Towler et al.
patent: 2002-237190 (2002-08-01), None
“The Next Generation of Content Addressable Memories,” MOSAID Technologies Incorporated, Sep. 1999, pp. 1-7.

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