Semiconductor memory

Details Semiconductor memory Semiconductor memory

2002-11-05

2004-04-13

Phan, Trong (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S149000, C365S230030

Reexamination Certificate

active

06721194

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a dynamic random access memory (DRAM) whose margin can be expanded by minimizing noise occurring in a memory cell array comprising single-intersection memory cells.
2. Description of the Related Art
DRAMs are generally used to reduce the area of a chip and hence minimize the manufacturing costs thereof.
FIG. 9A
shows a single-intersection memory cell array having memory cells connected at all intersections of word lines WL (WL
0
, WL
1
, WL
2
) and bit lines BL (BL
0
B, BL
0
T, BL
1
B, BL
1
T, BL
2
B, BL
2
T). Compared with known dual-intersection memory cell arrays having memory cells connected at only half of the intersections of word and bit lines, the area occupied by the single-intersection memory cell array can be reduced by 25%. Referring to
FIG. 9A
, there are shown sense amplifiers SA
0
, SA
1
, SA
2
, etc.
However, compared with the dual-intersection memory cell array, the single-intersection memory cell array has a drawback that the array noise increases during data reading. This obstructs practical use of the single-intersection memory cell array.
Moreover, even in the dual-intersection memory cell array, when a difference between capacitance levels of two parasitic capacitors formed between complementary bit lines and a word line gets so large that the noise cannot be canceled, the problem of increasing array noise persists.
FIG. 9B
shows the waveforms associated with the occurrence of one form of array noise comprising word line noise.
FIG. 9B
is illustrative of the case where the word line WL
0
is activated, high-level data is read and placed on the bit line BL
1
T, and low-level data is read and placed on bit lines BL
0
T and BL
2
T.
Where the amount of intelligence on the bit line BL
1
T has substantially decreased due to current leakage or any other reason, the signals with a large amount of intelligence on the bit lines BL
0
and BL
2
are amplified first. As indicated by dotted arrows in
FIG. 9A
, a potential difference between the bit line BL
0
(BL
0
T, BL
0
B) or BL
2
(BL
2
T, BL
2
B) and the bit line BL
1
(BL
1
T, BL
1
B) brings about a potential difference between the word line WL
0
and an adjoining one WL
1
, WL
2
or WL
3
due to a parasitic capacitor CBLWL formed between a bit line and word line. The potential difference returns to the bit line BL
1
via the parasitic capacitor CBLWL.
The amount of intelligence on the bit line BL
1
is so small that the signal is amplified slowly. If the amount of intelligence decreases because of an accompanying noise, the signal may be inverted incorrectly. A similar noise occurs because of a plate that is a counter electrode of a capacitor included in a memory cell or a substrate of a transistor included in the memory cell. Therefore, in order to put the single-intersection memory cell array to practical use, it is mandatory to minimize the array noise.
Referring to the pair of bit lines BL
1
T and BL
1
B, the array noise becomes the largest in the case where high-level data items (defined as 1s) or low-level data items (defined as 0s) are read onto all side-T bit lines BL
0
T, BL
2
T, etc.
FIG. 10
shows the configuration of a semiconductor memory in accordance with the related art in which the pattern of data items to be written in memory cells is encoded in order to reduce the array noise. Similar methods of reducing the array noise are described in, for example, JP-A No. 110967/1999 and the IEEE journal “Solid-state Circuits” (Vol. 34, No. 10, October 1999, pp.1391-1394).
In the semiconductor memory of the related art, bits are received in sequence via an input/output buffer IOB through input/output pins DQ. The bits are multiplexed by a multiplexer MUX and temporarily written in registers RE. At the same time, the number of bits received in sequence is counted using a burst counter BC. At this time, if the number of 1s occupies 25% or less or 75% or more, a flag FLG is set. This causes encoders EN to invert half of the bits. In this case, the number of bits constituting data placed on one word line WL is confined to the range from 25% to 75% of the number of received bits. Consequently, the array noise is reduced to 50% of the array noise occurring when received bits are 100% 1s or are 100% 0s.
FIG. 10
shows memory cells MC, sense amplifiers SA, bit lines BL, and a decoder DEC, and a selection signal SEL.
However, in the semiconductor memory having encoders of the related art, a flag bit is needed for each of data blocks that are received in sequence. If the number of bits received in sequence is small, the number of flag memory cells included in a chip increases and undesirably increases chip size.
Further, the number of bits received in sequence through the input/output pins DQ is counted using the burst counter BC. It is then determined whether the flag FLG should be set. Such determination takes a long time to make and undesirably increases the time required for the memory cycle.
Moreover, the criterion that the number of 1s occupies 25% or less or 75% or more used in the semiconductor memory having encoders of the related art is so complex that it undesirably increases the circuit scale and the area of a chip.
SUMMARY OF THE INVENTION
According to at least one preferred embodiment of the present invention, a semiconductor memory is provided comprising a plurality of memory cells wherein each memory cell is connected at one of the plurality of intersections of one of a plurality of word lines and one of a plurality of bit lines; a one-bit flag memory cell included for each word line; a plurality of sense amplifiers associated with the plurality of bit lines; a plurality of randomly accessible data registers holding writable data; an encoding control circuit that determines the ratio of the number of 1s contained in the writable data to the number of 0s contained therein; and encoders that write writable data items in sense amplifiers as they are or after inverting them according to the result of the determination made by the encoding control circuit.
Whenever external access is made to the semiconductor memory, the data registers are also accessed. When data items read from the data registers are written simultaneously in the memory cell array, the data items are encoded. When data items are read from the memory cells into the data registers, a flag is referenced in order to decode the data items. The encoders and encoding control circuit of the semiconductor memory are designed to perform these actions. Consequently, the array noise occurring during reading is minimized and the margin is maximized. The access time and size of the chip including the semiconductor memory are also minimized.


REFERENCES:
patent: 5050126 (1991-09-01), Tanaka et al.
patent: 5371711 (1994-12-01), Nakayama
patent: 5592407 (1997-01-01), Konishi et al.
patent: 6075735 (2000-06-01), Sugibayashi
patent: 6414893 (2002-07-01), Miyamoto
patent: 11-110967 (1997-10-01), None
patent: 2002-93158 (2000-09-01), None
Satoshi Utsugi, Masami Hanyu, Yoshinori Muramatsu and Tadahiko Sugibayashi, “Noncomplimentary Rewriting and Serial-Data Coding Scheme for Shared-Sense-Amplifier Open-Bit-Line DRAM”, IEEE Journal of Solid-State Circuits, vol. 34, No. 10, Oct. 1999, pp. 1391-1394.

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