Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-05-29
2004-05-11
Auduong, Gene (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185120, C365S185330
Reexamination Certificate
active
06735126
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrically rewritable nonvolatile semiconductor memory.
2. Description of the Related Art
A nonvolatile semiconductor memory such as a flash memory is capable of carrying out erase operation by an entire chip or by a sector.
FIG. 1
shows an example of a control circuit inside the semiconductor memory for erasing data by the sector. A sector decoder
1
activates any of sector selecting signals SEC
0
to SEC
255
according to address signals ADD (sector address). A sector latch circuit
2
includes latches SL
0
to SL
255
for latching the respective sector selecting signals SEC
0
to SEC
255
and outputting the latched signals as erase flag signals EFLG
0
to EFLG
255
. The latches SL
0
to SL
255
are formed corresponding to sectors of a memory array (not shown), respectively. The sectors corresponding to the erase flag signals EFLG
0
to EFLG
255
which are activated according to the sector selecting signals SEC
0
to SEC
255
are selected, and the data in these sectors are erased.
FIG. 2
shows the operation of erasing the data by the sector. In this example, the address signals ADD and data signals DQ are inputted in synchronization with a write enable signal /WE.
First, 555h (“h” indicates hexadecimal number) is supplied to the address signals ADD and AAh is supplied to the data signals DQ in a first bus cycle, and 2AAh is supplied to the address signals ADD and 55h is supplied to the data signals DQ in a second bus cycle so that an internal circuit of the flash memory is activated. Next, when 555h is supplied to the address signals ADD and 80h is supplied to the data signals DQ in a third bus cycle, the flash memory identifies that an erase command is supplied thereto, and starts the operation of the control circuit which controls the erase operation.
Thereafter, 555h and 2AAh are sequentially supplied to the address signals ADD, and AAh and 55h are sequentially supplied to the data signals DQ in fourth and fifth bus cycles. In erasing the sector, 30h (indicating the supply of a sector address SA) is supplied to the data signals DQ in a sixth bus cycle. At this time, the address signals ADD are supplied as a sector address SAO from which the data are erased. The sector decoder
1
shown in
FIG. 1
decodes the sector address SA. The sector latch circuit
2
latches the sector selecting signal SEC (any of SEC
0
to SEC
255
) outputted from the sector decoder
1
, and activates the erase flag signal EFLG.
In erasing a plurality of the sectors, the sector addresses SA and the data signals DQ (30h) are sequentially supplied in synchronization with the write enable signal /WE in and after a seventh bus cycle. The sector decoder
1
sequentially decodes the sector addresses SA, similarly to the above. The sector latch circuit
2
successively latches the sector selecting signals SEC (any of SEC
0
to SEC
255
) outputted from the sector decoder
1
, and activates the erase flag signals EFLG. Then, the erase operation is started after a predetermined period from the last-supplied command (sector address) so that the data of the sector which corresponds to the activated erase flag signal EFLG in the sector latch circuit
2
is erased. It should be mentioned that the first to sixth bus cycles are referred to as an input period for erase command and a period from the seventh bus cycle to the start of the erase operation is referred to as a time out period. Incidentally, when 10h is supplied to the data signals DQ in the sixth bus cycle, the flash memory carries out chip batch erasure for erasing the data of all the sectors after a predetermined period.
In order to erase the data of a plurality of the sectors in a conventional flash memory, it is necessary to input the sector addresses indicating the sectors one by one. It is apparent that in the future, the number of sectors increases as a storage capacity of the semiconductor memory such as the flash memory increases. For example, supposing that a capacity of one sector is 64k byte, the number of sectors of the 8M-bit (1M-word×8-bit) flash memory becomes 16. However, in the 256M-bit (32M-word×8-bit) flash memory, the number of the sectors becomes 512. In this case, for example, in selecting the 200 sectors from which the data are erased, the 200 bus cycles are necessary. Thus, when a memory capacity increases in the future, a time out period of great length is required in order to erase the data of a plurality of the sectors. When the number of the bus cycles for specifying the sectors from which the data are erased increases, a load of a system increases in instructing the semiconductor memory to carry out the erase operation. Further, a system program to be carried out by a CPU or the like which controls the semiconductor memory is complicated.
SUMMARY OF THE INVENTION
It is an object of the present invention to efficiently select a plurality of memory regions as minimum units for erasing data in a semiconductor memory having electrically rewritable nonvolatile memory cells.
It is another object of the present invention to reduce the load of a system for controlling the semiconductor memory and to simplify a control program.
According to one of the aspects of the semiconductor memory of the present invention, the semiconductor memory includes a plurality of memory blocks each having a predetermined number of memory regions being minimum erase units for erasing data. The respective memory regions include electrically rewritable nonvolatile memory cells. An erase selecting circuit selects all of the memory regions in one of the memory blocks selected by a first address signal supplied with an erase control signal, when the erase control signal supplied in response to an erase command indicates a first erase mode. An erase control circuit erases data of the memory regions selected by the erase selecting circuit. Namely, erasure of the data is carried out by the memory block when the erase control signal indicates the first erase mode. Since a plurality of the memory regions from which the data are erased can be selected simultaneously by one erase command, it is possible to reduce the number of input of the erase commands. Therefore, it is possible to simplify a system program to be carried out by a CPU or the like which controls the semiconductor memory. Further, since the number of cycles for selecting the memory regions from which the data are erased (input period for erase command) is reduced, it is possible to reduce the load of a system for instructing the semiconductor memory to carry out erase operation.
According to another aspect of the semiconductor memory of the present invention, the erase selecting circuit selects any one of the memory regions corresponding to a second address signal supplied with the erase control signal, when the erase control signal indicates a second erase mode. The erase control circuit erases the data of one memory region selected by the erase selecting circuit. Since the first or second erase mode is identified by the erase control signal, the memory regions to be erased can be selected by the memory block or by the memory region according to the erase control signal. As a result, the memory regions from which the data are erased can be selected efficiently with the smaller number of cycles.
According to another aspect of the semiconductor memory of the present invention, when the erase control signal changes a plurality of times in response to the erase command, the erase selecting circuit sequentially selects all of the memory regions or one of the memory regions in the selected memory block according to the change of the erase control signal. Thereafter, the erase control circuit erases data of the memory regions selected by the erase selecting circuit. Hence, all of the memory regions from which the data should be erased can be selected simultaneously by one erase command, and the data of these memory regions can be erased. The system which controls the semiconductor memory supplies, fo
Arent & Fox PLLC
Auduong Gene
Fujitsu Limited
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