Semiconductor memory

Details Semiconductor memory Semiconductor memory

2001-05-15

2002-04-16

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S063000

Reexamination Certificate

active

06373777

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor memories, and more particularly to a semiconductor device having two memory portions that are connected by a transfer bus of reduced size.
BACKGROUND OF THE INVENTION
Many computer systems can include a main memory. In order to maintain reasonable costs in such computer systems, main memories are typically composed of dynamic random access memories (DRAMs). DRAMs can be fabricated in a variety of configurations and sizes. In the past, general purpose (asynchronous) DRAMs could provide sufficient speed at a low enough cost to be used in a main memory.
More recently, however, computer operating speeds have begun to outpace the speed of general purpose DRAMS. In particular, processor speeds have outpaced the data transfer rates of general purpose DRAMs. To alleviate the disparities in processor rates and general purpose DRAM data transfer rates, many systems have employed a substorage device situated between a main memory and a processor. Such substorage devices are typically referred to as “cache” memories. A cache memory is typically a high-speed memory device, such as a static RAM (SRAM) or an emitter coupled logic bipolar RAM (ECLRAM), to name just a few examples. A cache memory can be integrated into a processor, or may be provided external to the processor.
Another variation in memory devices combines DRAMs and high speed cache-type RAMs on the same device. Such combination devices have been utilized in computer workstations and some personal computers. Such devices can include a main storage formed from a DRAM and a cache memory formed from a SRAM. Both the DRAM and SRAM are formed on the same semiconductor substrate. Such devices have been referred to as cache DRAMs or CDRAMs.
CDRAMs can be arranged to transfer data between the DRAM and SRAM portions in a bidirectional fashion. When a memory is accessed, if the requested data location is in the SRAM portion, the access can be considered a cache “hit.” If a requested data location is not in the SRAM portion, the access can be considered a cache “miss.” The requested data can then be retrieved from the DRAM. A drawback to conventional CDRAMs is that cache misses can introduce some delay into a data transfer operation.
Another drawback to such CDRAMs is the number of external pins that are utilized in such devices (pin count). Because the DRAM portion and SRAM portion have their own respective address pins, the number of pins on a CDRAM can be much larger than those of a conventional DRAM. Therefore, a CDRAM device is not easily utilized with typical DRAM controllers.
Yet another problem associated with conventional CDRAMs is the amount of area that may be needed to realize a data transfer circuit. Because the area available for such circuits can be limited, the number of transfer bus lines between a DRAM and SRAM portion can also be limited.
Due to the above constraints, the number of data bits that can be transferred at the same time between a DRAM portion and a SRAM portion on a CDRAM can be limited. Further, many conventional CDRAM approaches avoid placing transfer lines in the same area as column select lines. As a result, the number of transfer lines can further be limited by the width of such available areas. As a general rule, the smaller the number of bits that can be transferred between DRAM and SRAM portions, the lower hit rate of the cache. One skilled in the art would recognize that lower cache hit rates leads to slower overall data access operations for a CDRAM.
The current applicant has previously proposed a “virtual channel” memory. In particular, a virtual channel synchronous DRAM (VCSDRAM) has been disclosed in Japanese Patent Publication No. Hei 11-86559 that can increase the access speed of a SDRAM.
The above-described VCSDRAM can include a memory array of DRAM cells arranged into rows and columns. In addition to the memory array, the VCSDRAM can include a register array having a number of rows and columns. The number of rows and/or columns in the register array can be some ratio of the number of rows and/or columns in the memory array. The register array can provide a cache function in the row and or column directions, and can include SRAM cells.
The above-described VCSDRAM can have a number of applications. One particular advantageous application of a VCSDRAM is the storing and/or displaying of video data. Data can be stored within a memory cell as picture elements (pixels). Pixel data can then be read out in a successive fashion from the same region of the memory array. The pixel data can be amplified by a sense amplifier group corresponding to the memory array region. Particular sense amplifiers can then be selected to transfer data to the channel register by way of a transfer bus.
Referring now to
FIG. 6
, a VCSDRAM, such as that referred to above, is illustrated in a block diagram. The VCSDRAM is designated by the general reference character
600
, and is shown to include two cell regions, designated as
602
-
0
and
602
-
1
. The cell regions (
602
-
0
and
602
-
1
) can include a number of memory cells connected to digit lines, one of which is shown as
604
. As just one arrangement, the digit lines can be connected to memory cells in a column-wise direction.
A number of sense amplifiers, one of which is shown as item
606
, are situated adjacent to both cell regions (
602
-
0
and
602
-
1
). Sense amplifier
606
(and those sense amplifiers within its group) can be considered “cornmon” to both cell regions (
602
-
0
and
602
-
1
). At the other end of cell region
602
-
0
is another group of sense amplifiers, one of which is shown as item
608
. Further, at the other end of cell region
602
-
1
is a third group of sense amplifiers, one of which is shown as item
610
. In the arrangement of
FIG. 6
, sense amplifier
608
(and those sense amplifiers within its group) is dedicated to cell region
602
-
0
, and sense amplifier
610
(and those sense amplifiers within its group) is dedicated to cell region
602
-
1
.
The VCSDRAM
600
further includes a number of registers
614
-
0
to
614
-
2
disposed at one end of the cell regions (
602
-
0
and
602
-
1
). The registers (
614
-
0
to
614
-
2
) can be connected to the various sense amplifier groups by transfer bus lines, shown as
616
-
00
to
616
-
21
. Connections between the sense amplifiers and their associated transfer bus lines (
616
-
00
to
616
-
21
) can be conventional in nature, and are not shown in particular in FIG.
6
.
For example, transfer bus lines
616
-
20
/
21
can transfer data from sense amplifier
606
,
608
or
610
to channel register
614
-
2
. That is, one sense amplifier group can be activated, and thereby place data on the transfer bus lines (
616
-
00
to
616
-
21
) and into registers (
614
-
0
to
614
-
2
). Data stored in registers (
614
-
0
to
614
-
2
) can be transferred to external locations according to channel read and channel write commands.
In the arrangement of
FIG. 6
, signals SSU
1
, SSU
2
, SSM
1
, SSM
2
, SSD
1
and SSD
2
indicate sense amplifier selection signals. Sense amplifier selection signals can be applied to sense amplifier groups by way of select lines, shown as
618
-
00
/
01
,
618
-
10
/
11
, and
618
-
20
/
21
. In the arrangement of
FIG. 6
, sense amplifier groups can be conceptualized as including “even” sense amplifiers that alternate with “odd” sense amplifiers. Accordingly, select signal SSU
1
can select even sense amplifiers from the group that includes sense amplifier
608
, and select signal SSU
2
can select odd sense amplifiers. Along these same lines, select signal SSM
1
can select even sense amplifiers and SSM
2
can select odd sense amplifiers from the group that includes sense amplifier
606
, and select signal SSD
1
can select even sense amplifiers and SSD
2
can select odd sense amplifiers from the group that includes sense amplifier
610
.
Referring once again to
FIG. 6
, when the SSU
1
signal is activated, sense amplifier
608
can place data on transfer lines
616
-
20
/
21
.

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