Semiconductor memory

Details Semiconductor memory Semiconductor memory

2000-11-20

2002-05-07

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Floating gate

Multiple values

C365S185220, C365S185330, C365S201000

Reexamination Certificate

active

06385084

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory capable of executing a read test for stored contents comparatively easily, and more particularly to a nonvolatile semiconductor memory such as an electrically writable/erasable flash memory.
2. Description of the Background Art
In general, the production cost of a memory implies the total of the cost required for a wafer process, an assembly and a test. The cost of the test depends on how many chips can be tested per unit time by means of one tester. In order to reduce the test cost to produce a more inexpensive memory, accordingly, it is required that the prolongation of a test time caused by an increase in a storage capacity of the memory should be minimized even if the storage capacity of the memory is increased twofold to fourfold with an increase in the capacity.
In order to shorten a test time of the memory, the following should be implemented:
(1) a reduction in an operation time required for write, read or the like;
(2) development of a test pattern having a higher defect detecting capability; and
(3) development of a test mode capable of carrying out write/read at a higher speed.
Referring to (1), an increase in a speed of production has been required. Therefore, the test time tends to be shortened comparatively easily without a special contrivance through an enhancement in transistor performance by microfabrication and a reduction in a load capacity.
Referring to (2), there are various test patterns having high defect detecting capabilities. Typically, a checker board pattern can be taken as an example.
FIG. 95
is a diagram illustrating an example of the checker board pattern.
FIG. 95
shows a checker board pattern having one bit/cell (binary-value).
As shown in
FIG. 95
, a checker board pattern CHK
2
is a test pattern having a repetitive cycle of 2 bits in which adjacent bits always have a relationship of “0” and “1”. The checker board pattern CHK
2
can detect open (disconnection) and a short circuit of a word line, open and a short circuit of a bit line, and a defective short circuit of floating gates in a nonvolatile semiconductor memory represented by a flash memory.
FIG. 96
is a diagram illustrating a checker board pattern CHK
4
having 2 bits/cell (quaternary-value). As shown in
FIG. 96
, 2-bit patterns CHK
4
-A to CHK
4
-D are repeated every 4-bit repetitive cycle in order to correspond to the quaternary-value (2 bits/cell) to be multiple-valued storage through application of the checker board pattern CHK
2
shown in FIG.
95
.
FIG. 97
is a diagram illustrating a checker board pattern CHK
8
having 3 bits/cell (octal-value). As shown in
FIG. 97
, a 3-bit pattern is repeated every 8-bit repetitive cycle in order to correspond to the octal-value (3 bits/cell) to be multiple-valued storage.
In the checker board pattern CHK
4
and the checker board pattern CHK
8
, it is possible to detect a defective mode of the checker board pattern CHK
2
, and furthermore, to detect that all multiple-valued data can be written and read or not in the same word line and the same bit line.
Referring to (3), there have been various methods. In general, if a test mode is incorporated into a chip, a chip area tends to be increased due to an incorporated circuit. Consequently, a cost required for a wafer process is increased. Accordingly, in the case in which the test mode is to be incorporated into the chip, it is necessary to note that the total production cost should be minimized.
Next, the trend of a product of a flash memory and that of development will be described.
As an alternative to an EPROM (electrically writable nonvolatile semiconductor memory), a flash memory has spread for code storage. In recent years, a flash memory for mass data storage has spread more increasingly than the flash memory for code storage. In the case in which the flash memory for data storage carries out writing and reading randomly, it operates at a lower speed than that of the flash memory for code storage. However, in the case in which the flash memory for data storage carries out writing and reading sequentially, it can operate at a higher speed than that of the flash memory for code storage. The flash memory for data storage has had a larger capacity to exceed a DRAM through microfabrication of a processing pattern and a multiple-valued technique for storing multibit data in one memory cell.
Next, a test time for the flash memory will be described.
The flash memory for code storage has such a structure that a reading operation can be carried out at a much higher speed than a writing operation. Therefore, a time required for a read test can be almost ignored with respect to the whole test time. However, the flash memory for data storage carries out the writing operation at a higher speed and has a larger capacity than the flash memory for code storage. Therefore, the time required for the read test cannot be disregarded with respect to the whole test time.
For example, a 256 Mbit flash memory has a 16 Ksector structure in which a 2 Kbyte write/read unit (hereinafter referred to as a “sector”) is present for 16K. Approximately 50 &mgr;s is required for a reading head every sector (hereinafter referred to as a “1st access”) and 50 ns is required for subsequent data transfer every byte.
Accordingly, approximately 2.5 s ((50 &mgr;s+50 ns×2 Kbyte)·16 Ksector) is required for carrying out a read test in the whole area of the 256 Mbit flash memory.
In a probing check stage of a wafer state, furthermore, it is hard to carry out a read test with a 2nd access 50 ns of a product specification due to a resistance and a capacitance of a probe needle and a resistance and a capacitance of a probe card, and a test time is further increased.
In general, the flash memory has an automatic writing/erasing function. The automatic writing function implies a function of repeating a write pulse applying operation and an operation (hereinafter referred to as a “verify operation”) for deciding whether desirable data are written (or erased) to (or from) an object memory cell for writing in accordance with a logic circuit (hereinafter referred to as a “control circuit”) provided in an EEPROM, ending the repetition of the write pulse applying operation and the verify operation when it is decided that all the object memory cells store the desirable data and outputting a signal for giving, to the outside of the EEPROM, a notice that the writing operation (or the erasing operation) has been completed.
In order to decide whether “the contents stored in all the object memory cells are the desirable data”, an all latch deciding circuit (hereinafter referred to as an “ALL deciding circuit”) is provided. The ALL deciding circuit serves to decide that all sense latches in a sense latch group provided for storing the result of read of the memory cell are “1” or “0”.
FIG. 98
is a block diagram schematically showing a conventional ALL deciding circuit and a periphery thereof. In this specification, it is assumed that the case in which “1” is written to the memory cell is set to “write” and the case in which “0” is written to the memory cell is set to “erase”. Referring to
FIG. 98
, description will be given in which a left memory cell group
31
is referred to as an L mat
31
and a right memory cell group
32
is referred to as an R mat
32
.
As shown in
FIG. 98
, a sense latch group
33
is provided between the L mat
31
and the R mat
32
. The sense latch group
33
transmits and receives data in a sector unit to and from the L mat
31
or the R mat
32
. The latch data of the sense latch group
33
are output to an ALL deciding circuit
34
.
The ALL deciding circuit
34
receives control signals LorR, 0or1 and ENABLE from an external control CPU
35
and outputs a decision result ALL
34
to the control CPU
35
. “0”/“1” of the LorR designates reading from the L mat
31
/R mat
32
, “0”/“1” of the 0or1 designates write verify/erase verify, and “0”/“1” of the ENABLE designates inactivity/activity of the

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