Semiconductor memory

Details Semiconductor memory Semiconductor memory

2008-04-01

2008-04-01

Yoha, Connie C. (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230090, C365S221000

Reexamination Certificate

active

07352648

ABSTRACT:
At least one complete cell array having a predetermined memory capacity and an incomplete cell array having a capacity smaller than the predetermined memory capacity are arranged in one direction. The incomplete cell array is disposed closer to a signal control unit than the complete cell array. The signal control unit disposed on one-end side of a row of the cell arrays receives/outputs a signal from/to a global line. A read/write control unit disposed between the cell arrays controls data read/write from/to the cell arrays. The global line extends from one-end side of the row of the cell arrays to be connected to the read/write control unit. The global line is always wired on the short incomplete cell array, thereby reducing load capacitance and charge/discharge current thereof. This can reduce power consumption of a semiconductor memory, and shorten the access time thereof.

REFERENCES:
patent: 5524264 (1996-06-01), Shirota et al.
patent: 6925543 (2005-08-01), Takahashi et al.
patent: 6967882 (2005-11-01), Akiyoshi
patent: 2005-166098 (2005-06-01), None

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