Semiconductor memory

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

Reexamination Certificate

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Details

C365S189110

Reexamination Certificate

active

07952955

ABSTRACT:
A semiconductor memory is provided which includes a word line coupled to a transistor of a memory cell; a word driver configured to activate the word line; a first resistance portion configured to couple the word line to a low-level voltage line in accordance with an activation of the word line and to decouple the coupling after a first period in an activation period of the word line elapses; a second resistance portion configured to couple the word line to a high-level voltage line in a second period in the activation period; and a third resistance portion configured to couple the word line to the low-level voltage line in the second period, a resistance of the third resistance portion being higher than a resistance of the first resistance portion, wherein a high-level voltage of the word line in the second period is lower than that of the high-level voltage line.

REFERENCES:
patent: 5737275 (1998-04-01), Matthews et al.
patent: 7085175 (2006-08-01), Remington et al.
patent: 2007/0030741 (2007-02-01), Nii et al.
patent: 08-036881 (1996-02-01), None
patent: 2007-066493 (2007-03-01), None

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