Semiconductor memory

Details Semiconductor memory Semiconductor memory

1992-05-21

1993-07-13

Bowler, Alyssa H.

Static information storage and retrieval

Addressing

Sync/clocking

36518901, 365191, 365194, 365203, G11C 700, G11C 800

Patent

active

052280039

ABSTRACT:
A semiconductor memory adapted to receive a chip selection signal and address signal, composed of: a signal generating circuit for generating inner selection signals with respect to the chip selection signal, a pulse generating circuit for detecting any changes in the address signals and generating a pulse signal; and a pulse width changing circuit for inputting the pulse signal to output a control signal for precharging or equalizing the data lines of a memory cell array. The pulse width changing circuit outputs the control signal having a pulse whose pulse width corresponds to what is obtained by converting the pulse width of the pulse signal into a longer one when the inner selection signals are in the chip-selecting condition.

REFERENCES:
patent: 4337525 (1982-06-01), Akatsuka
patent: 4893282 (1990-01-01), Wada et al.
patent: 4916668 (1990-04-01), Matsui
patent: 4922122 (1990-05-01), Dubujet
patent: 4961172 (1990-10-01), Shubat et al.
patent: 4962487 (1990-10-01), Suzuki
patent: 4982366 (1991-01-01), Takemae
"Address Transition Detection Enhancement Circuit", IBM Technical Disclosure Bulletin, vol. 30, No. 8, Jan. 1988.

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