Semiconductor memory

Static information storage and retrieval – Addressing

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365105, G11C 800

Patent

active

046086722

ABSTRACT:
An electronic device is provided which includes first and second memory arrays, each capable of storing data at locations therein, and an address decoder positioned between the first and second memory arrays for decoding address signals input thereto and corresponding to the locations. The address decoder is advantageously configured as a set of ISL gates or MESFET logic gates. It is further advantageous to form the memory arrays of Schottky diodes which, when employed with the ISL configuration for an address decoder, utilizes the same Schottky diode in the memory arrays as are utilized in the ISL gates. A further refinement provides a precharged circuit for each bit line.

REFERENCES:
patent: 3886531 (1975-05-01), McNeill
patent: 4096584 (1978-06-01), Owen, III et al.
patent: 4208730 (1980-06-01), Dingwall et al.
patent: 4276617 (1981-06-01), Le
patent: 4347585 (1982-08-01), Eardley
patent: 4393472 (1983-07-01), Shimada et al.
patent: 4394752 (1983-07-01), Boudon et al.
J. F. Gunn et al., "A Bipolar 16K ROM Utilizing Schottky Diode Cells", 1977 IEEE International Solid-State Circuits Conference, Session X:LSI Technology, Feb. 1977.
J. Lohstroh Article "ISL, A Fast and Dense Low-Power Logic, Made in a Standard Schottky Process, Journal of Solid-State Circuits, vol. SC-14, No. 3, Jun. 1979.
Honeywell's Preliminary Interim Phase 1 Technical Report.

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