1977-08-17
1978-11-21
Wojciechowicz, Edward J.
357 22, 357 23, 357 41, 357 45, H01L 2906
Patent
active
041268814
ABSTRACT:
A semiconductor memory has storage cells composed of MOS selector transistors operated by a drive line and storage capacitors connected to selector transistors. The selector transistors are constructed in accordance with the V-MOS technique. A semiconductor substrate is highly doped with atoms of one conductivity type and carries a buried layer highly doped with atoms of the opposite conductivity type. An epitaxial layer, weakly doped with atoms of the one conductivity type is carried over the buried layer and the semiconductor substrate. A second layer, highly doped with atoms of the opposite conductivity type, is carried over the epitaxial layer above the buried layer. A V-shaped groove divides the second layer into two sub-portions in the region of the storage cells and extends into the buried layer and a conductor path is disposed in the groove.
REFERENCES:
patent: 4003036 (1977-01-01), Jenne
Hofmann Rudiger
VON Basse Paul-Werner
Siemens Aktiengesellschaft
Wojciechowicz Edward J.
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