Semiconductor memory

Static information storage and retrieval – Format or disposition of elements

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Details

365 63, 365190, 365203, 365207, G11C 502, G11C 700

Patent

active

060381582

ABSTRACT:
The objective is to realize a semiconductor memory capable of avoiding an increase in the load of the sense amplifiers, easily realizing a large capacity and high integration of the memory, reducing the current consumption by the bit lines, and improving the access speed. Because the levels of the selection signal lines SHUS1, SHUE1, SHDS1, and SHDE1 are set by the control circuit, only one of the aforementioned four selection signal lines is selected at the time of memory access, other selection signal lines are held in unselect status, and the sense amplifiers in the sense amplifier bank SB1a and prescribed bit line pairs or extended bit line pairs are connected to each other by response in order to carry out read or write; thus, the load of the sense amplifiers can be reduced, and high speed, large capacity, and high integration can be achieved.

REFERENCES:
patent: 4570241 (1986-02-01), Arzubi
patent: 5107459 (1992-04-01), Chu et al.
patent: 5555203 (1996-09-01), Shiratake et al.

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