Semiconductor memory

Details Semiconductor memory Semiconductor memory

1998-09-18

2000-06-27

Nguyen, Viet Q.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523001, 36523006, 365231, 36518516, 36518511, 36518517, G11C 800

Patent

active

060814748

ABSTRACT:
In a semiconductor memory, four bit line diffused interconnections 1 connected to two bit line terminals D0 and D1 through bank selection transistors BT1 and BT2 are connected to drains of memory cells of four column pairs, respectively, and four bit line diffused interconnections 2 connected to one virtual ground line terminal VG1 through bank selection transistors BT3 to BT6 are connected to sources of memory cells of the four column pairs. The bank selection transistors BT1 to BT6 are so located that each of the bit line diffused interconnections 1 is connected to a corresponding one of the bit line terminals D0 and D1 through only one bank selection transistor and each of bit line diffused interconnections 2 is connected to the virtual ground line terminal VG1 through only one bank selection transistor. Thus, data can be surely read from a selected memory cell at a high speed. At the time of elevating the integrated density, it is easy to locate and pattern metal interconnections connected to the bit line terminal and the virtual ground line terminal.

REFERENCES:
patent: 5268861 (1993-12-01), Hotta
patent: 5392233 (1995-02-01), Iwase
patent: 5590068 (1996-12-01), Bergemont
patent: 5621697 (1997-04-01), Weng et al.
patent: 5726929 (1998-03-01), Suminaga et al.
patent: 5825683 (1998-10-01), Chang
patent: 5875128 (1999-02-01), Ishizuka
patent: 5909405 (1999-06-01), Lee et al.

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