Semiconductor memory

Details Semiconductor memory Semiconductor memory

1992-08-31

1994-11-08

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Sync/clocking

36518909, 365207, 365226, 365104, G11C 702, G11C 700

Patent

active

053633407

ABSTRACT:
A semiconductor memory whose sense amplifier having a bias circuit and a charging circuit is provided. The bias circuit includes a first MOSFET whose source is connected to a digit line, a second MOSFET provided between a power source and the first MOSFET and becoming a load of the first MOSFET, and a first inverter whose input terminal and output terminal are connected respectively to the source and gate of the first MOSFET. The charging circuit includes a third MOSFET whose source is connected to the source of the first MOSFET, a second inverter whose input terminal and output terminal are connected respectively to the source and gate of the third MOSFET, and a fourth MOSFET provided between the drain of the third MOSFET and the power source and receiving through the gate thereof an output signal of an address transition detector which detects an address change and generates a pulse signal. The source of the first MOSFET is made an input terminal and a connecting point of the first MOSFET and a second MOSFET is made an output terminal of the sense amplifier. The potential amplitude of an output signal of the sense amplifier is same as that of the conventional one, so that the sense amplifier can be operated speedily and stably when a selected digit line due to address change is charged.

REFERENCES:
patent: 5022003 (1991-06-01), Kohno
patent: 5056063 (1991-10-01), Santin et al.
patent: 5132937 (1992-07-01), Tuda et al.

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