Semiconductor memory

Details Semiconductor memory Semiconductor memory

1996-07-30

1998-06-16

Popek, Joseph A.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36518905, 365233, G11C 800

Patent

active

057682127

ABSTRACT:
In the semiconductor memory of this invention, a first unit of data that is inputted by means of the same standard clock as an external address and that is inputted to a chip prior to determination of the internal address signal that is prefetched is latched to all latch circuits into which this data may be latched. After an address is determined by the next standard clock, second and succeeding units of data inputted to the chip are inputted only to latch circuits that are latched in accordance with address signals. In this way, even if internal address signal processing has not been completed at the time of latching the first unit of data, both the first unit of data and second and succeeding units of data can be latched in prefetch circuits designated by addresses from the outside.

REFERENCES:
patent: 4775990 (1988-10-01), Kamuro et al.
patent: 5610864 (1997-03-01), Manning
H.-J. Yoo, et al., "A 150MHz 8-Banks 256M Synchronous DRAM with Wave Pipelining Methods", 1995 IEEE International Solid-State Circuits Conference, ISSCC95, Session 14, DRAM, Paper FA 14.4, pp. 250-251.

Affiliated with

Also associated with

Rating

Semiconductor memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1734234