Semiconductor memory

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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Details

36523001, 36523003, G11C 800

Patent

active

056318731

ABSTRACT:
A block selection signal generating circuit (70) outputs block selection signals (BSa, BSb, BSc, BSd). When the changeover signal (NORMAL) is "L", only one of the block selection signals (BSa, BSb, BSc, BSd) becomes "H" if the value of the column address (CA<12:11>) as the block address are "00", "01", "10", "11", respectively. The block address is obtained ahead of the row address RA<12:0>. Only one of the sense amplifiers (40a to 40d) corresponding to the column specified by the block address is driven to save the power consumption.

REFERENCES:
patent: 4344005 (1982-08-01), Stewart
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patent: 5175835 (1992-12-01), Beighe et al.
patent: 5335204 (1994-08-01), Matsuo et al.
1990 IEEE International Solid-State Circuits Conference, pp. 230-231, Feb. 16, 1990, Yasuhiro Konishi, et al., "A 38ns 4Mb DRAM With A Battery Back-up (BBU)Mode".

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