Active solid-state devices (e.g. – transistors – solid-state diode – With means to absorb or localize unwanted impurities or...
Reexamination Certificate
2001-07-06
2003-10-28
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
With means to absorb or localize unwanted impurities or...
C257S131000, C257S607000, C257S608000, C257S609000, C257S610000, C257S611000, C257S612000
Reexamination Certificate
active
06639327
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor members and semiconductor devices which are useful for silicon-on-insulator (SOI) devices and to methods for manufacturing these semiconductor members and devices. Specifically, the present invention relates to semiconductor members and semiconductor devices which are capable of gettering heavy metal elements and to methods for manufacturing these semiconductor members and devices.
2. Description of the Related Art
Known semiconductor members include, for example, substrates having at least two laminated layers composed of different types of semiconductor materials and SOI substrates each composed of a semiconductor layer laminated on an insulating layer.
In bulk Si wafers, ultra-high purity crystals can be obtained by typical wafer manufacturing methods such as the Czpchralski process (CZ process), since segregation coefficients of heavy metal elements in Si crystals are very low.
In contrast, SOI wafers use bulk Si as a starting material and inevitably undergo a heat treatment process for the formation of an insulating layer or for the smoothing of the surface in any manufacturing method. In the heat treatment process, heavy metal elements contained in a furnace or in a heater tend to flow into the stream of a gas at high temperatures and possibly diffuse into an SOI wafer during its manufacture.
When ion implantation is used in the manufacture, a member in an evacuated housing or in the passage of implanted ions is irradiated with ions, the component elements of the member are ionized, and the resulting ions can be implanted into an SOI wafer during its manufacture, together with a principle ion to be implanted into the wafer.
Heavy metal elements entering in an Si crystal freely diffuse in the crystal during a treatment at high temperatures, but gradually become limited in diffusion in a cooling process, and are ultimately fixed by the formation of silicide compounds by a reaction with Si or the formation of oxides by a reaction with oxygen. For example, Ni and Cu are known to form silicides to thereby accumulate in the circumference of minute defects in the Si crystal, as described by Takao Abe in “Silicon: Crystal Growth and Wafer Processing”, pp. 233, Baifukan. Fe is also known to form a silicide in the interface between Si and SiO
2
to thereby segregate when it diffuses in an Si crystal having an oxide film, as described in J. Appl. Phys., 83, 583 (1998).
Such heavy metal elements may form defects in Si crystals and may form deep levels in an Si band gap in some cases. If a defect is formed in a single-crystal semiconductor layer as an active device region, a chip manufactured in this region becomes defective. The formation of a deep level by such a heavy metal element causes changes in electrical properties of the chip to thereby decrease the yield of chips. The ratio of the defects or level-forming regions to the size of the device increases with further enhanced miniaturization and higher density packing of devices, and very strong demands have been made to remedy contamination with heavy metal elements.
Such a device manufacturing operation includes a number of processes, and it is difficult to always maintain all the processes under normal conditions. Accordingly, unexpected abnormalities may occur in some processes to thereby allow heavy metal elements to contaminate a wafer during its manufacture. It takes many days to manufacture devices, and if an abnormality in an intermediate process is found after finished devices are obtained, all the wafers in the manufacturing operation at that time potentially are defective.
To avoid this problem, in bulk Si wafers, a gettering site for gettering heavy metal elements is formed in the back or inside of the wafer to thereby prevent unexpected contamination of the wafer with heavy metal elements during the manufacturing process.
The following gettering techniques are well known and are effectively used to remove heavy metal elements from the active device region in the device process.
1. Gettering heavy metal elements inside the wafer by intrinsic gettering utilizing the precipitation of oxygen in Z wafers;
2. Gettering heavy metal elements in the back of the wafer by extrinsic gettering such as backside damage, the formation of a polysilicon film, and the diffusion of phosphorus.
SOI wafers are also starting materials of the device process as bulk Si, and in these wafers, increasing demands have been made to remedy contamination with heavy metal elements. SOI wafer fabricators have made intensive efforts to remedy heavy metal contamination mainly along a course to avoid contamination with heavy metal elements during the manufacturing process.
However, heavy metal element contamination, which may occur in the heat treatment process, cannot be significantly prevented, and the heavy metal contamination levels of all the product SOI wafers cannot be strictly ensured. Additionally, if the wafer is contaminated with heavy metal elements through the heat treatment or ion implantation during the manufacturing process of an SOI wafer, the SOI wafer must have a gettering site gettering these heavy metal elements.
Even if SOI wafers having a perfect crystal quality are manufactured, the chip yield may be decreased due to heavy metal element contamination when heavy metal elements contaminate the wafers in the heat treatment operation of the device process.
In SOI wafers, a semiconductor element or device such as a transistor is formed in a limited region, that is, an ultrathin single-crystal Si region on an insulating layer (oxide film). If this region is free from contamination with heavy metal elements and the oxide film as an insulating layer is uniformly formed, the chip yield can be prevented from decreasing due to heavy metal element contamination.
The manufacturing methods of SOI wafers are roughly classified under two groups: a separation by ion-implanted oxygen (SIMOX) process in which oxygen ions are implanted into an Si single-crystal substrate to thereby form an insulating layer; and a bonding process in which two different semiconductor substrates are bonded and a single-crystal semiconductor layer is formed by polishing or separation.
The oxide film (insulating layer) in the bonded SOI wafer is composed of a uniform thermal oxide film and is believed to have a higher quality than that of the oxide film of the SIMOX SOI wafer formed by oxygen ion implantation and annealing. Additionally, the SIMOX SOI wafer tends to have crystal defects in the single-crystal semiconductor layer induced by oxygen ion implantation. Accordingly, the bonding process is believed to more easily manufacture high-quality SOI wafers than the SIMOX process.
In the SIMOX process, it is known that oxidation induced stacking faults (OSFs) are formed immediately below the insulating layer simultaneously with the formation of the insulating layer. Cu and Ni, which may contaminate the wafer in the heat treatment process, are captured by OSFs, and the single-crystal semiconductor layer becomes resistant to heavy metal element contamination. This means that a gettering site is spontaneously formed without any extra process in the SIMOX manufacturing process and that the SIMOX process is superior in cost to the bonding process.
In the bonded SOI wafers, attempts have also been made to form a gettering site inside the substrate to thereby getter heavy metal elements.
For example, in a method described in Japanese Patent Laid-Open No. 6-163862, a layer in which a high concentration of phosphorus atoms is diffused, an ion implantation layer, or a lattice mismatching layer is formed on one of two substrates to be bonded, and the formed layer plays a role as a gettering site.
In a method described in Japanese Patent Laid-Open No. 8-293589, the substrate side of a wafer is subjected to a two-stage heat treatment to thereby form an oxygen precipitate, and dislocations are introduced in the vicinity of the surface of the wafer by heat stress in a cooling operati
Honma Noriaki
Ito Masataka
Momoi Kazutaka
Sato Nobuhiko
Yonehara Takao
Soward Ida M.
Zarabian Amir
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