Stock material or miscellaneous articles – All metal or with adjacent metals – Composite; i.e. – plural – adjacent – spatially distinct metal...
Reexamination Certificate
2006-03-07
2006-03-07
Stein, Stephen (Department: 1775)
Stock material or miscellaneous articles
All metal or with adjacent metals
Composite; i.e., plural, adjacent, spatially distinct metal...
C428S446000, C428S448000, C428S304400
Reexamination Certificate
active
07008701
ABSTRACT:
This invention provides an SOI substrate manufacturing method using a transfer method (bonding and separation). A separation layer (12) is formed on a silicon substrate (11). A silicon layer (13), SiGe layer (14), silicon layer (15′), and insulating layer (21) are sequentially formed on the resultant structure to prepare a first substrate (10′). This first substrate (10′) is bonded to a second substrate (30). The bonded substrate stack is separated into two parts at the separation layer (12). Next, Ge in the SiGe layer (14) is diffused into the silicon layer (13) by hydrogen annealing. With this process, a strained SOI substrate having the SiGe layer on the insulating layer (21) and a strained silicon layer on the SiGe layer is obtained.
REFERENCES:
patent: 5461243 (1995-10-01), Ek et al.
patent: 5759898 (1998-06-01), Ek et al.
patent: 5882987 (1999-03-01), Srikrishnan
patent: 6106613 (2000-08-01), Sato et al.
patent: 6143628 (2000-11-01), Sato
patent: 6171982 (2001-01-01), Sato
patent: 6221738 (2001-04-01), Sakaguchi
patent: 6323108 (2001-11-01), Kub et al.
patent: 6335269 (2002-01-01), Sato
patent: 6375738 (2002-04-01), Sato
patent: 6407367 (2002-06-01), Ito
patent: 6413874 (2002-07-01), Sato
patent: 6524935 (2003-02-01), Canaperi et al.
patent: 6537846 (2003-03-01), Lee et al.
patent: 6613678 (2003-09-01), Sakaguchi et al.
patent: 0 651 439 (1995-05-01), None
patent: 2000-243946 (2000-09-01), None
patent: WO 98/52216 (1998-11-01), None
patent: 01/11930 (2001-02-01), None
“A Novel Fabrication Technique of Ultra-Thin and Relaxed SiGe Buffer Layers with High Ge Content for Sub-100 nm Strained Silicon-On-Insulator MOSFETRs”, T. Tezuka et al., Extended Abstracts of the 2000 International Conference on Solid State Devices and Materials, Sendai, 2000, pp. 472-473.
“Design of SiGe/Buried Oxide Layered Structure to Form Highly Strained Si Layer on Insulator for SOI MOSFETs”, N. Sugiyama et al., Extended Abstracts of the 2000 International Conference on Solid State Devices and Materials, Sendai, 2000, pp. 474-475.
Hobart, K. D., et al, “Fabrication of SOI substrates with ultra-thin Si layers”,Electronic Letters, Jun. 11, 1998, vol. 34, No. 12.
Notsu Kazuya
Sato Nobuhiko
Canon Kabushiki Kaisha
Stein Stephen
LandOfFree
Semiconductor member manufacturing method and semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor member manufacturing method and semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor member manufacturing method and semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3578742