Radiation imagery chemistry: process – composition – or product th – Radiation modifying product or process of making – Radiation mask
Reexamination Certificate
2001-03-13
2003-05-27
Young, Christopher G. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Radiation modifying product or process of making
Radiation mask
C430S022000, C257S797000, C438S975000
Reexamination Certificate
active
06569579
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the manufacture of semiconductor devices and more particularly to semiconductor wafer and photomask alignment.
BACKGROUND ART
In recent years, semiconductor devices such as integrated circuits and large scale integrated circuits have decreased in size and increased in density such that higher accuracy has been required of the manufacturing equipment, and particularly the exposure equipment, in which the circuit pattern of a mask or a reticle is transferred onto a semiconductor wafer. Photo-patterning of the wafers requires precise positioning of a reticle or mask relative to the wafer being processed. To achieve such precise positioning, the exact orientation or location of the wafer must be known such that the mask can be precisely placed. This is typically accomplished by moving the wafer beneath fixed optics, which rely on photosensors to determine the wafer's precise location relative to a table on which the wafer rests and moves relative to the optics. The optics are directed toward the wafer to determine location of predetermined patterns provided in the wafer at at least two discrete locations, such that wafer orientation is determined. With such known, the photomask and wafer can be precisely positioned in a desired relative orientation for processing.
After positioning, a photosensitive material deposited on the wafer is exposed to light or radiation to transfer the pattern of the photomask to the wafer. In step-and-repeat type equipment in which each exposure helps in the formation of a layer of a chip, the wafer is caused to effect stepping by a predetermined distance and then the circuit pattern of the mask is again exposed. Particularly in reduction projection type exposure equipment (steppers), have become the main current of the exposure apparatuses of this kind. In this step-and-repeat system, the wafer is placed on a two-dimensionally movable stage and positioned relative to the projected image of the circuit pattern of the mask and therefore, the projected image and each chip on the wafer can be precisely superposed one upon the other. Also, in the case of the reduction projection type exposure apparatus, there are two methods, namely, the through-the-lens type alignment method in which alignment marks provided on a mask or a reticle and marks attendant to the chips on a wafer are directly observed or detected through a projection lens to thereby accomplish alignment, and the off-axis type alignment method in which alignment of an entire wafer is effected by the use of an alignment microscope provided at a predetermined distance from a projection lens and the wafer is fed to just beneath the projection lens. Generally, the through-the-lens system has a merit that the super-position accuracy is high because alignment is effected for each chip on the wafer, but suffers from a problem that the exposure processing time of a wafer is long. In the case of the off-axis system, once alignment of the entire wafer has been completed, the wafer need only be caused to effect stepping in accordance with the arrangement of the chips and therefore, the exposure processing time is shortened. However, the alignment of each chip is not effected and therefore, satisfactory super-position accuracy has not always been obtained under the influence of the expansion and contraction of the wafer, the rotation error of the wafer on the stage, the degree of orthogonality of movement of the stage itself, etc.
The wafer alignment patterns typically include discrete areas on the semiconductor substrate, which are initially patterned to form multiple series of precisely configured parallel lines. In subsequent processing of the wafer, sometimes these wafer alignment patterns are masked such that they are not subjected to the specific processing, while other times they are left unmasked and are accordingly processed. For example, in some instances it is desirable to provide a planarized layer of a highly reflective or opaque material. Such a layer, because it is planarized, would not repeat the underlying pattern and substantially all incident light would be reflected away or absorbed. In such instance, the underlying alignment pattern would be lost. Accordingly in such instances, the wafer alignment pattern area would not be masked such that etching of such materials would not occur over the alignment patterns.
Where planarization does not occur or where a planarized layer is suitably light transmissive to reveal the underlying pattern, the wafer alignment areas are typically masked during processing. Not masking of the wafer alignment pattern area throughout processing is typically not desired, as such would adversely effect overall global planarity of the wafer and eventually result in the wafer alignment patterns being received in deep holes or caverns. This would adversely affect the utility of the patterns and lead to other wafer processing problems. For example, whether an alignment step is masked or not masked during a photo exposure depends on several factors. These include, 1) the ability to see the alignment step at the next photo step; 2) the impact on the rest of the wafer, such as cracking and planarity; and 3) consistency in being able to get good alignment at all subsequent photo-processing steps.
The increasing circuit density and vertical integration associated therewith has lead to increasing utilization of planarizing steps to assure an overall planar wafer which is easier to process. This, however, has placed difficult constraints upon photomask alignment relative to the wafers being processed. Specifically, contrasts provided by illuminating the wafer with incident light must rely in part upon differences in light intensity resulting from internal reflections off of a buried structure. This presents only minor problems for a single layer of surface planarized material, or for a stack of surface planarized transparent materials where each has a similar index of refraction and the underlying film has high reflectance. However where a stack of two planarized layers of different material having substantially different indexes of refraction is utilized, obtaining adequate contrast for ultimate wafer and photomask alignment becomes considerably more complex.
At present, there is no way to assure image placement of the first photomask layer with respect to the zero photomask layer, or global alignment mask. Hence it is not possible to check the overlay accuracy of the first photomask layer and non-correctable overlay errors occur at the second photomask layer. For example, if there is a trapezoidal error at the first mask layer (due to a faulty reticle or reticle stage), subsequent layers aligning to the first layer will exhibit complex overlay errors (high
3
sigma) which are difficult to compensate due to large residual errors.
A method of assuring accurate image placement of the first photomask so that subsequent layers would have greater overlay accuracy and minimal non-correctable overlay errors has been long sought but have equally long eluded those skilled in the art.
DISCLOSURE OF THE INVENTION
The present invention provides an exposure apparatus for a semiconductor wafer which includes a light source, a body containing the light source, and an illumination optical system for directing light from the light source to the semiconductor wafer. A holder in the body holds a reticle and a zero layer reticle is disposed between the illumination optical system and the light source for masking light from the light source. The zero layer reticle has a pellicle frame and a pellicle film with a zero layer image placement indicator thereon which when aligned with a box on a first layer image assures alignment among the zero layer reticle, the first layer reticle, and the semiconductor wafer.
The present invention further provides a zero layer reticle which has a pellicle frame and a pellicle film with a zero layer image placement indicator thereon which when aligned with a box on a first layer image assures alignmen
Ghosh Amit
Tan Yew Kong
Chartered Semiconductor Manufacturing Ltd.
Ishimaru Mikio
Young Christopher G.
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